debug/programs/trigger.S

   1 #include "../../env/encoding.h"
   2
   3 #if XLEN == 64
   4 # define LREG ld
   5 # define SREG sd
   6 # define REGBYTES 8
   7 #else
   8 # define LREG lw
   9 # define SREG sw
  10 # define REGBYTES 4
  11 #endif
  12
  13 #undef MCONTROL_TYPE
  14 #undef MCONTROL_DMODE
  15 #if __riscv_xlen == 64
  16 # define MCONTROL_TYPE    (0xf<<(64-4))
  17 # define MCONTROL_DMODE   (1<<(64-5))
  18 #else
  19 # define MCONTROL_TYPE    (0xf<<(32-4))
  20 # define MCONTROL_DMODE   (1<<(32-5))
  21 #endif
  22
  23         .global         main
  24
  25         .section        .text
  26 main:
  27
  28         la      a0, data
  29         li      t0, 0
  30 just_before_read_loop:
  31         li      t2, 16
  32 read_loop:
  33         lw      t1, 0(a0)
  34         addi    t0, t0, 1
  35         addi    a0, a0, 4
  36         blt     t0, t2, read_loop
  37
  38         la      a0, data
  39 just_before_write_loop:
  40         li      t0, 1
  41 write_loop:
  42         sw      t0, 0(a0)
  43         addi    t0, t0, 1
  44         addi    a0, a0, 4
  45         blt     t0, t2, write_loop
  46
  47         j       main_exit
  48
  49 write_store_trigger:
  50         li      a0, (1<<6) | (1<<1)
  51         li      a1, 0xdeadbee0
  52         jal     write_triggers
  53         la      a0, data
  54         jal     read_triggers
  55
  56 write_load_trigger:
  57         li      a0, (1<<6) | (1<<0)
  58         li      a1, 0xfeedac00
  59         jal     write_triggers
  60         la      a0, data
  61         jal     read_triggers
  62
  63 // Clear triggers so the next test can use them.
  64 clear_triggers:
  65         li      a0, 0
  66         jal     write_triggers
  67
  68 main_exit:
  69         li      a0, 0
  70         j       _exit
  71
  72 write_triggers:
  73         // a0: value to write to each tdata1
  74         // a1: value to write to each tdata2
  75         li      t0, 0
  76 2:
  77         csrw    CSR_TSELECT, t0
  78         csrr    t1, CSR_TSELECT
  79         bne     t0, t1, 1f
  80         addi    t0, t0, 1
  81         csrw    CSR_TDATA2, a1
  82         csrw    CSR_TDATA1, a0
  83         j       2b
  84 1:      ret
  85
  86 read_triggers:
  87         // a0: address where data should be written
  88         li      t0, 0
  89 2:
  90         csrw    CSR_TSELECT, t0
  91         csrr    t1, CSR_TSELECT
  92         bne     t0, t1, 1f
  93         addi    t0, t0, 1
  94         csrr    t1, CSR_TDATA1
  95         SREG    t1, 0(a0)
  96         csrr    t1, CSR_TDATA2
  97         SREG    t1, REGBYTES(a0)
  98         addi    a0, a0, 2*REGBYTES
  99         j       2b
 100 1:      SREG    zero, 0(a0)
 101         ret
 102
 103         .data
 104 data:   .word   0x40
 105         .word   0x41
 106         .word   0x42
 107         .word   0x43
 108         .word   0x44
 109         .word   0x45
 110         .word   0x46
 111         .word   0x47
 112         .word   0x48
 113         .word   0x49
 114         .word   0x4a
 115         .word   0x4b
 116         .word   0x4c
 117         .word   0x4d
 118         .word   0x4e
 119         .word   0x4f