debug/targets.py

   1 import os.path
   2 import tempfile
   3
   4 import testlib
   5
   6 class Target(object):
   7     name = "name"
   8     xlen = 0
   9     directory = None
  10     timeout_sec = 2
  11     temporary_files = []
  12     temporary_binary = None
  13     openocd_config = []
  14     use_fpu = False
  15     misa = None
  16
  17     def __init__(self, server_cmd, sim_cmd, isolate):
  18         self.server_cmd = server_cmd
  19         self.sim_cmd = sim_cmd
  20         self.isolate = isolate
  21
  22     def target(self):
  23         """Start the target, eg. a simulator."""
  24         pass
  25
  26     def server(self):
  27         """Start the debug server that gdb connects to, eg. OpenOCD."""
  28         if self.openocd_config:
  29             return testlib.Openocd(server_cmd=self.server_cmd, config=self.openocd_config)
  30         else:
  31             raise NotImplementedError
  32
  33     def compile(self, *sources):
  34         binary_name = "%s_%s-%d" % (
  35                 self.name,
  36                 os.path.basename(os.path.splitext(sources[0])[0]),
  37                 self.xlen)
  38         if self.isolate:
  39             self.temporary_binary = tempfile.NamedTemporaryFile(
  40                     prefix=binary_name + "_")
  41             binary_name = self.temporary_binary.name
  42             Target.temporary_files.append(self.temporary_binary)
  43         march = "rv%dima" % self.xlen
  44         if self.use_fpu:
  45             march += "fd"
  46         if self.extensionSupported("c"):
  47             march += "c"
  48         testlib.compile(sources +
  49                 ("programs/entry.S", "programs/init.c",
  50                     "-I", "../env",
  51                     "-march=%s" % march,
  52                     "-T", "targets/%s/link.lds" % (self.directory or self.name),
  53                     "-nostartfiles",
  54                     "-mcmodel=medany",
  55                     "-DXLEN=%d" % self.xlen,
  56                     "-o", binary_name),
  57                 xlen=self.xlen)
  58         return binary_name
  59
  60     def extensionSupported(self, letter):
  61         # target.misa is set by testlib.ExamineTarget
  62         return self.misa & (1 << (ord(letter.upper()) - ord('A')))
  63
  64 class SpikeTarget(Target):
  65     # pylint: disable=abstract-method
  66     directory = "spike"
  67     ram = 0x80010000
  68     ram_size = 5 * 1024 * 1024
  69     instruction_hardware_breakpoint_count = 4
  70     reset_vector = 0x1000
  71     openocd_config = "targets/%s/openocd.cfg" % directory
  72
  73 class Spike64Target(SpikeTarget):
  74     name = "spike64"
  75     xlen = 64
  76     use_fpu = True
  77
  78     def target(self):
  79         return testlib.Spike(self.sim_cmd, halted=True)
  80
  81 class Spike32Target(SpikeTarget):
  82     name = "spike32"
  83     xlen = 32
  84
  85     def target(self):
  86         return testlib.Spike(self.sim_cmd, halted=True, xlen=32)
  87
  88 class FreedomE300Target(Target):
  89     name = "freedom-e300"
  90     xlen = 32
  91     ram = 0x80000000
  92     ram_size = 16 * 1024
  93     instruction_hardware_breakpoint_count = 2
  94     openocd_config = "targets/%s/openocd.cfg" % name
  95
  96 class HiFive1Target(FreedomE300Target):
  97     name = "HiFive1"
  98     openocd_config = "targets/%s/openocd.cfg" % name
  99
 100 class FreedomE300SimTarget(Target):
 101     name = "freedom-e300-sim"
 102     xlen = 32
 103     timeout_sec = 6000
 104     ram = 0x80000000
 105     ram_size = 256 * 1024 * 1024
 106     instruction_hardware_breakpoint_count = 2
 107     openocd_config = "targets/%s/openocd.cfg" % name
 108
 109     def target(self):
 110         return testlib.VcsSim(simv=self.sim_cmd, debug=False)
 111
 112 class FreedomU500Target(Target):
 113     name = "freedom-u500"
 114     xlen = 64
 115     ram = 0x80000000
 116     ram_size = 16 * 1024
 117     instruction_hardware_breakpoint_count = 2
 118     openocd_config = "targets/%s/openocd.cfg" % name
 119
 120 class FreedomU500SimTarget(Target):
 121     name = "freedom-u500-sim"
 122     xlen = 64
 123     timeout_sec = 6000
 124     ram = 0x80000000
 125     ram_size = 256 * 1024 * 1024
 126     instruction_hardware_breakpoint_count = 2
 127     openocd_config = "targets/%s/openocd.cfg" % name
 128
 129     def target(self):
 130         return testlib.VcsSim(simv=self.sim_cmd, debug=False)
 131
 132 targets = [
 133         Spike32Target,
 134         Spike64Target,
 135         FreedomE300Target,
 136         FreedomU500Target,
 137         FreedomE300SimTarget,
 138         FreedomU500SimTarget,
 139         HiFive1Target]
 140
 141 def add_target_options(parser):
 142     group = parser.add_mutually_exclusive_group(required=True)
 143     for t in targets:
 144         group.add_argument("--%s" % t.name, action="store_const", const=t,
 145                 dest="target")
 146     parser.add_argument("--sim_cmd",
 147             help="The command to use to start the actual target (e.g. "
 148             "simulation)")
 149     parser.add_argument("--server_cmd",
 150             help="The command to use to start the debug server (e.g. OpenOCD)")
 151
 152     xlen_group = parser.add_mutually_exclusive_group()
 153     xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen",
 154             help="Force the target to be 32-bit.")
 155     xlen_group.add_argument("--64", action="store_const", const=64, dest="xlen",
 156             help="Force the target to be 64-bit.")
 157
 158     parser.add_argument("--isolate", action="store_true",
 159             help="Try to run in such a way that multiple instances can run at "
 160             "the same time. This may make it harder to debug a failure if it "
 161             "does occur.")