Merge pull request #34 from richardxia/use-port-randomization
[riscv-tests.git] / debug / targets.py
1 import os.path
2 import tempfile
3
4 import testlib
5
6 class Target(object):
7 name = "name"
8 xlen = 0
9 directory = None
10 timeout_sec = 2
11 temporary_files = []
12 temporary_binary = None
13 openocd_config = []
14
15 def __init__(self, cmd, run, isolate):
16 self.cmd = cmd
17 self.run = run
18 self.isolate = isolate
19
20 def target(self):
21 """Start the target, eg. a simulator."""
22 pass
23
24 def server(self):
25 """Start the debug server that gdb connects to, eg. OpenOCD."""
26 if self.openocd_config:
27 return testlib.Openocd(cmd=self.cmd, config=self.openocd_config)
28 else:
29 raise NotImplementedError
30
31 def compile(self, *sources):
32 binary_name = "%s_%s-%d" % (
33 self.name,
34 os.path.basename(os.path.splitext(sources[0])[0]),
35 self.xlen)
36 if self.isolate:
37 self.temporary_binary = tempfile.NamedTemporaryFile(
38 prefix=binary_name + "_")
39 binary_name = self.temporary_binary.name
40 Target.temporary_files.append(self.temporary_binary)
41 testlib.compile(sources +
42 ("programs/entry.S", "programs/init.c",
43 "-I", "../env",
44 "-T", "targets/%s/link.lds" % (self.directory or self.name),
45 "-nostartfiles",
46 "-mcmodel=medany",
47 "-o", binary_name),
48 xlen=self.xlen)
49 return binary_name
50
51 class SpikeTarget(Target):
52 # pylint: disable=abstract-method
53 directory = "spike"
54 ram = 0x80010000
55 ram_size = 5 * 1024 * 1024
56 instruction_hardware_breakpoint_count = 4
57 reset_vector = 0x1000
58
59 class Spike64Target(SpikeTarget):
60 name = "spike64"
61 xlen = 64
62
63 def server(self):
64 return testlib.Spike(self.cmd, halted=True)
65
66 class Spike32Target(SpikeTarget):
67 name = "spike32"
68 xlen = 32
69
70 def server(self):
71 return testlib.Spike(self.cmd, halted=True, xlen=32)
72
73 class FreedomE300Target(Target):
74 name = "freedom-e300"
75 xlen = 32
76 ram = 0x80000000
77 ram_size = 16 * 1024
78 instruction_hardware_breakpoint_count = 2
79 openocd_config = "targets/%s/openocd.cfg" % name
80
81 class FreedomE300SimTarget(Target):
82 name = "freedom-e300-sim"
83 xlen = 32
84 timeout_sec = 240
85 ram = 0x80000000
86 ram_size = 256 * 1024 * 1024
87 instruction_hardware_breakpoint_count = 2
88 openocd_config = "targets/%s/openocd.cfg" % name
89
90 def target(self):
91 return testlib.VcsSim(simv=self.run, debug=False)
92
93 class FreedomU500Target(Target):
94 name = "freedom-u500"
95 xlen = 64
96 ram = 0x80000000
97 ram_size = 16 * 1024
98 instruction_hardware_breakpoint_count = 2
99 openocd_config = "targets/%s/openocd.cfg" % name
100
101 class FreedomU500SimTarget(Target):
102 name = "freedom-u500-sim"
103 xlen = 64
104 timeout_sec = 240
105 ram = 0x80000000
106 ram_size = 256 * 1024 * 1024
107 instruction_hardware_breakpoint_count = 2
108 openocd_config = "targets/%s/openocd.cfg" % name
109
110 def target(self):
111 return testlib.VcsSim(simv=self.run, debug=False)
112
113 targets = [
114 Spike32Target,
115 Spike64Target,
116 FreedomE300Target,
117 FreedomU500Target,
118 FreedomE300SimTarget,
119 FreedomU500SimTarget]
120
121 def add_target_options(parser):
122 group = parser.add_mutually_exclusive_group(required=True)
123 for t in targets:
124 group.add_argument("--%s" % t.name, action="store_const", const=t,
125 dest="target")
126 parser.add_argument("--run",
127 help="The command to use to start the actual target (e.g. "
128 "simulation)")
129 parser.add_argument("--cmd",
130 help="The command to use to start the debug server.")
131
132 xlen_group = parser.add_mutually_exclusive_group()
133 xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen",
134 help="Force the target to be 32-bit.")
135 xlen_group.add_argument("--64", action="store_const", const=64, dest="xlen",
136 help="Force the target to be 64-bit.")
137
138 parser.add_argument("--isolate", action="store_true",
139 help="Try to run in such a way that multiple instances can run at "
140 "the same time. This may make it harder to debug a failure if it "
141 "does occur.")