debug/targets.py

   1 import os.path
   2 import tempfile
   3
   4 import testlib
   5
   6 class Target(object):
   7     name = "name"
   8     xlen = 0
   9     directory = None
  10     timeout_sec = 2
  11     temporary_files = []
  12     temporary_binary = None
  13     openocd_config = []
  14     use_fpu = False
  15     misa = None
  16
  17     def __init__(self, server_cmd, sim_cmd, isolate):
  18         self.server_cmd = server_cmd
  19         self.sim_cmd = sim_cmd
  20         self.isolate = isolate
  21
  22     def target(self):
  23         """Start the target, eg. a simulator."""
  24         pass
  25
  26     def server(self):
  27         """Start the debug server that gdb connects to, eg. OpenOCD."""
  28         if self.openocd_config:
  29             return testlib.Openocd(server_cmd=self.server_cmd,
  30                     config=self.openocd_config)
  31         else:
  32             raise NotImplementedError
  33
  34     def compile(self, *sources):
  35         binary_name = "%s_%s-%d" % (
  36                 self.name,
  37                 os.path.basename(os.path.splitext(sources[0])[0]),
  38                 self.xlen)
  39         if self.isolate:
  40             self.temporary_binary = tempfile.NamedTemporaryFile(
  41                     prefix=binary_name + "_")
  42             binary_name = self.temporary_binary.name
  43             Target.temporary_files.append(self.temporary_binary)
  44         march = "rv%dima" % self.xlen
  45         if self.use_fpu:
  46             march += "fd"
  47         if self.extensionSupported("c"):
  48             march += "c"
  49         testlib.compile(sources +
  50                 ("programs/entry.S", "programs/init.c",
  51                     "-I", "../env",
  52                     "-march=%s" % march,
  53                     "-T", "targets/%s/link.lds" % (self.directory or self.name),
  54                     "-nostartfiles",
  55                     "-mcmodel=medany",
  56                     "-DXLEN=%d" % self.xlen,
  57                     "-o", binary_name),
  58                 xlen=self.xlen)
  59         return binary_name
  60
  61     def extensionSupported(self, letter):
  62         # target.misa is set by testlib.ExamineTarget
  63         if self.misa:
  64             return self.misa & (1 << (ord(letter.upper()) - ord('A')))
  65         else:
  66             return False
  67
  68 class SpikeTarget(Target):
  69     # pylint: disable=abstract-method
  70     instruction_hardware_breakpoint_count = 4
  71     reset_vector = 0x1000
  72
  73 class Spike64Target(SpikeTarget):
  74     name = "spike64"
  75     directory = name
  76     xlen = 64
  77     use_fpu = True
  78     # Would like to use 0x7fffffffffff0000 because it crosses the 0x8000...
  79     # boundary, but spike doesn't support that in the code where it generates
  80     # the reset vector.
  81     ram = 0x1212340000
  82     ram_size = 0x10000000
  83     openocd_config = "targets/%s/openocd.cfg" % directory
  84
  85     def target(self):
  86         return testlib.Spike(self)
  87
  88 class Spike32Target(SpikeTarget):
  89     name = "spike32"
  90     directory = name
  91     xlen = 32
  92     ram = 0x10000000
  93     ram_size = 0x10000000
  94     openocd_config = "targets/%s/openocd.cfg" % directory
  95
  96     def target(self):
  97         return testlib.Spike(self)
  98
  99 class FreedomE300Target(Target):
 100     name = "freedom-e300"
 101     xlen = 32
 102     ram = 0x80000000
 103     ram_size = 16 * 1024
 104     instruction_hardware_breakpoint_count = 2
 105     openocd_config = "targets/%s/openocd.cfg" % name
 106
 107 class HiFive1Target(FreedomE300Target):
 108     name = "HiFive1"
 109     openocd_config = "targets/%s/openocd.cfg" % name
 110
 111 class FreedomE300SimTarget(Target):
 112     name = "freedom-e300-sim"
 113     xlen = 32
 114     timeout_sec = 6000
 115     ram = 0x80000000
 116     ram_size = 256 * 1024 * 1024
 117     instruction_hardware_breakpoint_count = 2
 118     openocd_config = "targets/%s/openocd.cfg" % name
 119
 120     def target(self):
 121         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 122
 123 class FreedomU500Target(Target):
 124     name = "freedom-u500"
 125     xlen = 64
 126     ram = 0x80000000
 127     ram_size = 16 * 1024
 128     instruction_hardware_breakpoint_count = 2
 129     openocd_config = "targets/%s/openocd.cfg" % name
 130
 131 class FreedomU500SimTarget(Target):
 132     name = "freedom-u500-sim"
 133     xlen = 64
 134     timeout_sec = 6000
 135     ram = 0x80000000
 136     ram_size = 256 * 1024 * 1024
 137     instruction_hardware_breakpoint_count = 2
 138     openocd_config = "targets/%s/openocd.cfg" % name
 139
 140     def target(self):
 141         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
 142
 143 targets = [
 144         Spike32Target,
 145         Spike64Target,
 146         FreedomE300Target,
 147         FreedomU500Target,
 148         FreedomE300SimTarget,
 149         FreedomU500SimTarget,
 150         HiFive1Target]
 151
 152 def add_target_options(parser):
 153     group = parser.add_mutually_exclusive_group(required=True)
 154     for t in targets:
 155         group.add_argument("--%s" % t.name, action="store_const", const=t,
 156                 dest="target")
 157     parser.add_argument("--sim_cmd",
 158             help="The command to use to start the actual target (e.g. "
 159             "simulation)")
 160     parser.add_argument("--server_cmd",
 161             help="The command to use to start the debug server (e.g. OpenOCD)")
 162
 163     xlen_group = parser.add_mutually_exclusive_group()
 164     xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen",
 165             help="Force the target to be 32-bit.")
 166     xlen_group.add_argument("--64", action="store_const", const=64, dest="xlen",
 167             help="Force the target to be 64-bit.")
 168
 169     parser.add_argument("--isolate", action="store_true",
 170             help="Try to run in such a way that multiple instances can run at "
 171             "the same time. This may make it harder to debug a failure if it "
 172             "does occur.")