Merge pull request #21 from sifive/add_freedom_sim_targets
[riscv-tests.git] / debug / targets / freedom-u500-sim / link.lds
1 OUTPUT_ARCH( "riscv" )
2
3 SECTIONS
4 {
5 . = 0x80000000;
6 .text :
7 {
8 *(.text.entry)
9 *(.text)
10 }
11
12 /* data segment */
13 .data : { *(.data) }
14
15 .sdata : {
16 _gp = . + 0x800;
17 *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
18 *(.srodata*)
19 *(.sdata .sdata.* .gnu.linkonce.s.*)
20 }
21
22 /* bss segment */
23 .sbss : {
24 *(.sbss .sbss.* .gnu.linkonce.sb.*)
25 *(.scommon)
26 }
27 .bss : { *(.bss) }
28
29 __malloc_start = .;
30 . = . + 512;
31
32 /* End of uninitalized data segement */
33 _end = .;
34 }