767d22963de48571f4efe9bfa35bce9350897f94
[riscv-tests.git] / debug / targets / freedom-u500-sim / openocd.cfg
1 adapter_khz 10000
2
3 source [find interface/jtag_vpi.cfg]
4
5 set _CHIPNAME riscv
6 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
7
8 set _TARGETNAME $_CHIPNAME.cpu
9 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
10
11 #reset_config trst_and_srst separate
12 # Stupid long so I can see the LEDs
13 #adapter_nsrst_delay 2000
14 #jtag_ntrst_delay 1000
15 #
16 init
17 #reset
18
19 halt