Made some progress towards working with spike.
[riscv-tests.git] / debug / targets / spike / entry.S
1 #ifndef ENTRY_S
2 #define ENTRY_S
3
4 #include "encoding.h"
5
6 #define STACK_SIZE ((1 << 12) - 128)
7
8 #ifdef __riscv64
9 # define LREG ld
10 # define SREG sd
11 # define REGBYTES 8
12 #else
13 # define LREG lw
14 # define SREG sw
15 # define REGBYTES 4
16 #endif
17
18 .section .text.entry
19 .globl _start
20 _start:
21 j handle_reset
22
23 nmi_vector:
24 j nmi_vector
25
26 trap_vector:
27 j trap_entry
28
29 handle_reset:
30 la t0, trap_entry
31 csrw mtvec, t0
32 csrwi mstatus, 0
33 csrwi mideleg, 0
34 csrwi medeleg, 0
35 csrwi mie, 0
36
37 # initialize global pointer
38 la gp, _gp
39
40 # initialize stack pointer
41 la sp, stack_top
42
43 # perform the rest of initialization in C
44 j _init
45
46 trap_entry:
47 addi sp, sp, -32*REGBYTES
48
49 SREG x1, 1*REGBYTES(sp)
50 SREG x2, 2*REGBYTES(sp)
51 SREG x3, 3*REGBYTES(sp)
52 SREG x4, 4*REGBYTES(sp)
53 SREG x5, 5*REGBYTES(sp)
54 SREG x6, 6*REGBYTES(sp)
55 SREG x7, 7*REGBYTES(sp)
56 SREG x8, 8*REGBYTES(sp)
57 SREG x9, 9*REGBYTES(sp)
58 SREG x10, 10*REGBYTES(sp)
59 SREG x11, 11*REGBYTES(sp)
60 SREG x12, 12*REGBYTES(sp)
61 SREG x13, 13*REGBYTES(sp)
62 SREG x14, 14*REGBYTES(sp)
63 SREG x15, 15*REGBYTES(sp)
64 SREG x16, 16*REGBYTES(sp)
65 SREG x17, 17*REGBYTES(sp)
66 SREG x18, 18*REGBYTES(sp)
67 SREG x19, 19*REGBYTES(sp)
68 SREG x20, 20*REGBYTES(sp)
69 SREG x21, 21*REGBYTES(sp)
70 SREG x22, 22*REGBYTES(sp)
71 SREG x23, 23*REGBYTES(sp)
72 SREG x24, 24*REGBYTES(sp)
73 SREG x25, 25*REGBYTES(sp)
74 SREG x26, 26*REGBYTES(sp)
75 SREG x27, 27*REGBYTES(sp)
76 SREG x28, 28*REGBYTES(sp)
77 SREG x29, 29*REGBYTES(sp)
78 SREG x30, 30*REGBYTES(sp)
79 SREG x31, 31*REGBYTES(sp)
80
81 csrr a0, mcause
82 csrr a1, mepc
83 mv a2, sp
84 jal handle_trap
85 csrw mepc, a0
86
87 # Remain in M-mode after mret
88 li t0, MSTATUS_MPP
89 csrs mstatus, t0
90
91 LREG x1, 1*REGBYTES(sp)
92 LREG x2, 2*REGBYTES(sp)
93 LREG x3, 3*REGBYTES(sp)
94 LREG x4, 4*REGBYTES(sp)
95 LREG x5, 5*REGBYTES(sp)
96 LREG x6, 6*REGBYTES(sp)
97 LREG x7, 7*REGBYTES(sp)
98 LREG x8, 8*REGBYTES(sp)
99 LREG x9, 9*REGBYTES(sp)
100 LREG x10, 10*REGBYTES(sp)
101 LREG x11, 11*REGBYTES(sp)
102 LREG x12, 12*REGBYTES(sp)
103 LREG x13, 13*REGBYTES(sp)
104 LREG x14, 14*REGBYTES(sp)
105 LREG x15, 15*REGBYTES(sp)
106 LREG x16, 16*REGBYTES(sp)
107 LREG x17, 17*REGBYTES(sp)
108 LREG x18, 18*REGBYTES(sp)
109 LREG x19, 19*REGBYTES(sp)
110 LREG x20, 20*REGBYTES(sp)
111 LREG x21, 21*REGBYTES(sp)
112 LREG x22, 22*REGBYTES(sp)
113 LREG x23, 23*REGBYTES(sp)
114 LREG x24, 24*REGBYTES(sp)
115 LREG x25, 25*REGBYTES(sp)
116 LREG x26, 26*REGBYTES(sp)
117 LREG x27, 27*REGBYTES(sp)
118 LREG x28, 28*REGBYTES(sp)
119 LREG x29, 29*REGBYTES(sp)
120 LREG x30, 30*REGBYTES(sp)
121 LREG x31, 31*REGBYTES(sp)
122
123 addi sp, sp, 32*REGBYTES
124 mret
125
126 .bss
127 .align 4
128 stack_bottom:
129 .skip STACK_SIZE
130 stack_top:
131 #endif