08af9dc40ad12439ce70e8fd196fdf43191ccd0c
1 #ifndef _ENV_PHYSICAL_SINGLE_CORE_H
2 #define _ENV_PHYSICAL_SINGLE_CORE_H
6 //-----------------------------------------------------------------------
8 //-----------------------------------------------------------------------
10 #define RVTEST_RV64U \
14 #define RVTEST_RV64UF \
19 #define RVTEST_RV64UV \
25 #define RVTEST_RV32U \
30 #define RVTEST_RV32UF \
36 #define RVTEST_RV32UV \
43 #define RVTEST_RV64S \
47 #define RVTEST_32_ENABLE \
48 clearpcr status, SR_S64 \
50 #define RVTEST_FP_ENABLE \
51 setpcr status, SR_EF; \
58 #define RVTEST_VEC_ENABLE \
59 setpcr status, SR_EV; \
66 #define RISCV_MULTICORE_DISABLE \
67 mfpcr a0, hartid; 1: bnez a0, 1b; \
71 #define RVTEST_CODE_BEGIN \
76 RISCV_MULTICORE_DISABLE; \
80 //-----------------------------------------------------------------------
82 //-----------------------------------------------------------------------
84 #define RVTEST_CODE_END \
86 //-----------------------------------------------------------------------
88 //-----------------------------------------------------------------------
104 //-----------------------------------------------------------------------
105 // Data Section Macro
106 //-----------------------------------------------------------------------
108 #define RVTEST_DATA_BEGIN EXTRA_DATA
109 #define RVTEST_DATA_END
113 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
114 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: