add first RV32 tests
[riscv-tests.git] / env / p / riscv_test.h
1 #ifndef _ENV_PHYSICAL_SINGLE_CORE_H
2 #define _ENV_PHYSICAL_SINGLE_CORE_H
3
4 //-----------------------------------------------------------------------
5 // Begin Macro
6 //-----------------------------------------------------------------------
7
8 #define RVTEST_RV64U \
9
10 #define RVTEST_RV32U \
11 clearpcr cr0, 0x80
12
13 #define RVTEST_RV64S \
14
15 #define RVTEST_FP_ENABLE \
16 setpcr cr0, 2; \
17 mfpcr a0, cr0; \
18 and a0, a0, 2; \
19 beqz a0, 1f; \
20 mtfsr x0; \
21 1:
22
23 #define RVTEST_VEC_ENABLE \
24 mfpcr a0, cr0; \
25 ori a0, a0, 4; \
26 mtpcr a0, cr0; \
27 li a0, 0xff; \
28 mtpcr a0, cr18; \
29
30 #define RVTEST_CODE_BEGIN \
31 .text; \
32 .align 4; \
33 .global _start; \
34 _start: \
35 RVTEST_FP_ENABLE \
36 RVTEST_VEC_ENABLE \
37 mfpcr a0, cr10; 1: bnez a0, 1b; \
38
39 //-----------------------------------------------------------------------
40 // End Macro
41 //-----------------------------------------------------------------------
42
43 #define RVTEST_CODE_END \
44
45 //-----------------------------------------------------------------------
46 // Pass/Fail Macro
47 //-----------------------------------------------------------------------
48
49 #define RVTEST_PASS \
50 fence; \
51 li x1, 1; \
52 mtpcr x1, cr30; \
53 1: b 1b; \
54
55 #define RVTEST_FAIL \
56 fence; \
57 beqz x28, 1f; \
58 sll x28, x28, 1; \
59 or x28, x28, 1; \
60 mtpcr x28, cr30; \
61 1: b 1b; \
62
63 //-----------------------------------------------------------------------
64 // Data Section Macro
65 //-----------------------------------------------------------------------
66
67 #define RVTEST_DATA_BEGIN
68 #define RVTEST_DATA_END
69
70 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
71 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
72
73 #endif