env/p/riscv_test.h

   1 #ifndef _ENV_PHYSICAL_SINGLE_CORE_H
   2 #define _ENV_PHYSICAL_SINGLE_CORE_H
   3
   4 #include "../pcr.h"
   5 #include "../hwacha_xcpt.h"
   6
   7 //-----------------------------------------------------------------------
   8 // Begin Macro
   9 //-----------------------------------------------------------------------
  10
  11 #define RVTEST_RV64U                                                    \
  12   .macro init;                                                          \
  13   .endm
  14
  15 #define RVTEST_RV64UF                                                   \
  16   .macro init;                                                          \
  17   RVTEST_FP_ENABLE;                                                     \
  18   .endm
  19
  20 #define RVTEST_RV64UV                                                   \
  21   .macro init;                                                          \
  22   RVTEST_FP_ENABLE;                                                     \
  23   RVTEST_VEC_ENABLE;                                                    \
  24   .endm
  25
  26 #define RVTEST_RV32U                                                    \
  27   .macro init;                                                          \
  28   RVTEST_32_ENABLE;                                                     \
  29   .endm
  30
  31 #define RVTEST_RV32UF                                                   \
  32   .macro init;                                                          \
  33   RVTEST_32_ENABLE;                                                     \
  34   RVTEST_FP_ENABLE;                                                     \
  35   .endm
  36
  37 #define RVTEST_RV32UV                                                   \
  38   .macro init;                                                          \
  39   RVTEST_32_ENABLE;                                                     \
  40   RVTEST_FP_ENABLE;                                                     \
  41   RVTEST_VEC_ENABLE;                                                    \
  42   .endm
  43
  44 #define RVTEST_RV64S                                                    \
  45   .macro init;                                                          \
  46   .endm
  47
  48 #define RVTEST_32_ENABLE                                                \
  49   clearpcr status, SR_S64                                               \
  50
  51 #define RVTEST_FP_ENABLE                                                \
  52   setpcr status, SR_EF;                                                 \
  53   mfpcr a0, status;                                                     \
  54   and   a0, a0, SR_EF;                                                  \
  55   bnez  a0, 2f;                                                         \
  56   RVTEST_PASS;                                                          \
  57 2:fssr x0;                                                              \
  58
  59 #define RVTEST_VEC_ENABLE                                               \
  60   setpcr status, SR_EA;                                                 \
  61   mfpcr a0, status;                                                     \
  62   and   a0, a0, SR_EA;                                                  \
  63   bnez  a0, 2f;                                                         \
  64   RVTEST_PASS;                                                          \
  65 2:                                                                      \
  66
  67 #define RISCV_MULTICORE_DISABLE                                         \
  68         mfpcr a0, hartid; 1: bnez a0, 1b;                               \
  69
  70 #define EXTRA_INIT
  71
  72 #define RVTEST_CODE_BEGIN                                               \
  73         .text;                                                          \
  74         .align  4;                                                      \
  75         .global _start;                                                 \
  76 _start:                                                                 \
  77         RISCV_MULTICORE_DISABLE;                                        \
  78         init;                                                           \
  79         EXTRA_INIT;                                                     \
  80
  81 //-----------------------------------------------------------------------
  82 // End Macro
  83 //-----------------------------------------------------------------------
  84
  85 #define RVTEST_CODE_END                                                 \
  86
  87 //-----------------------------------------------------------------------
  88 // Pass/Fail Macro
  89 //-----------------------------------------------------------------------
  90
  91 #define RVTEST_PASS                                                     \
  92         fence;                                                          \
  93         li  x1, 1;                                                      \
  94         mtpcr x1, tohost;                                               \
  95 1:      b 1b;                                                           \
  96
  97 #define RVTEST_FAIL                                                     \
  98         fence;                                                          \
  99         beqz x28, 1f;                                                   \
 100         sll x28, x28, 1;                                                \
 101         or x28, x28, 1;                                                 \
 102         mtpcr x28, tohost;                                              \
 103 1:      b 1b;                                                           \
 104
 105 //-----------------------------------------------------------------------
 106 // Data Section Macro
 107 //-----------------------------------------------------------------------
 108
 109 #define RVTEST_DATA_BEGIN EXTRA_DATA
 110 #define RVTEST_DATA_END
 111
 112 #define EXTRA_DATA
 113
 114 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
 115 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
 116
 117 #endif