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use RVTEST_RV64UF macro for FPU tests
[riscv-tests.git] / env / pt / riscv_test.h
1 #ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
2 #define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
3
4 #include "pcr.h"
5
6 //-----------------------------------------------------------------------
7 // Begin Macro
8 //-----------------------------------------------------------------------
9
10 #define RVTEST_RV64U \
11
12 #define RVTEST_RV64UF \
13 RVTEST_RV64U; \
14 RVTEST_FP_ENABLE
15
16 #define RVTEST_FP_ENABLE \
17 setpcr cr0, 2; \
18 mfpcr a0, cr0; \
19 and a0, a0, 2; \
20 bnez a0, 2f; \
21 RVTEST_PASS; \
22 2:mtfsr x0; \
23
24 #define RVTEST_VEC_ENABLE \
25 mfpcr a0, cr0; \
26 ori a0, a0, 4; \
27 mtpcr a0, cr0; \
28 li a0, 0xff; \
29 mtpcr a0, cr18; \
30
31 #define RVTEST_CODE_BEGIN \
32 .text; \
33 .align 4; \
34 .global _start; \
35 _start: \
36 RVTEST_FP_ENABLE \
37 RVTEST_VEC_ENABLE \
38 mfpcr a0, cr10; 1: bnez a0, 1b; \
39 ENABLE_TIMER_INTERRUPT \
40
41 //-----------------------------------------------------------------------
42 // End Macro
43 //-----------------------------------------------------------------------
44
45 #define RVTEST_CODE_END \
46 XCPT_HANDLER \
47
48 //-----------------------------------------------------------------------
49 // Pass/Fail Macro
50 //-----------------------------------------------------------------------
51
52 #define RVTEST_PASS \
53 fence; \
54 li x1, 1; \
55 mtpcr x1, cr30; \
56 1: b 1b; \
57
58 #define RVTEST_FAIL \
59 fence; \
60 beqz x28, 1f; \
61 sll x28, x28, 1; \
62 or x28, x28, 1; \
63 mtpcr x28, cr30; \
64 1: b 1b; \
65
66 //-----------------------------------------------------------------------
67 // Data Section Macro
68 //-----------------------------------------------------------------------
69
70 #define RVTEST_DATA_BEGIN \
71 .align 3; \
72 regspill: \
73 .dword 0xdeadbeefcafebabe; \
74 .dword 0xdeadbeefcafebabe; \
75 .dword 0xdeadbeefcafebabe; \
76 .dword 0xdeadbeefcafebabe; \
77 .dword 0xdeadbeefcafebabe; \
78 .dword 0xdeadbeefcafebabe; \
79 .dword 0xdeadbeefcafebabe; \
80 .dword 0xdeadbeefcafebabe; \
81 .dword 0xdeadbeefcafebabe; \
82 .dword 0xdeadbeefcafebabe; \
83 .dword 0xdeadbeefcafebabe; \
84 .dword 0xdeadbeefcafebabe; \
85 .dword 0xdeadbeefcafebabe; \
86 .dword 0xdeadbeefcafebabe; \
87 .dword 0xdeadbeefcafebabe; \
88 .dword 0xdeadbeefcafebabe; \
89 .dword 0xdeadbeefcafebabe; \
90 .dword 0xdeadbeefcafebabe; \
91 .dword 0xdeadbeefcafebabe; \
92 .dword 0xdeadbeefcafebabe; \
93 .dword 0xdeadbeefcafebabe; \
94 .dword 0xdeadbeefcafebabe; \
95 .dword 0xdeadbeefcafebabe; \
96 .dword 0xdeadbeefcafebabe; \
97 evac: \
98 .dword 0xdeadbeefcafebabe; \
99 .dword 0xdeadbeefcafebabe; \
100 .dword 0xdeadbeefcafebabe; \
101 .dword 0xdeadbeefcafebabe; \
102 .dword 0xdeadbeefcafebabe; \
103 .dword 0xdeadbeefcafebabe; \
104 .dword 0xdeadbeefcafebabe; \
105 .dword 0xdeadbeefcafebabe; \
106 .dword 0xdeadbeefcafebabe; \
107 .dword 0xdeadbeefcafebabe; \
108 .dword 0xdeadbeefcafebabe; \
109 .dword 0xdeadbeefcafebabe; \
110 .dword 0xdeadbeefcafebabe; \
111 .dword 0xdeadbeefcafebabe; \
112 .dword 0xdeadbeefcafebabe; \
113 .dword 0xdeadbeefcafebabe; \
114 .dword 0xdeadbeefcafebabe; \
115 .dword 0xdeadbeefcafebabe; \
116 .dword 0xdeadbeefcafebabe; \
117 .dword 0xdeadbeefcafebabe; \
118 .dword 0xdeadbeefcafebabe; \
119 .dword 0xdeadbeefcafebabe; \
120 .dword 0xdeadbeefcafebabe; \
121 .dword 0xdeadbeefcafebabe; \
122 .dword 0xdeadbeefcafebabe; \
123 .dword 0xdeadbeefcafebabe; \
124 .dword 0xdeadbeefcafebabe; \
125 .dword 0xdeadbeefcafebabe; \
126 .dword 0xdeadbeefcafebabe; \
127 .dword 0xdeadbeefcafebabe; \
128 .dword 0xdeadbeefcafebabe; \
129 .dword 0xdeadbeefcafebabe; \
130
131 #define RVTEST_DATA_END
132
133 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
134 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
135
136 //-----------------------------------------------------------------------
137 // Misc
138 //-----------------------------------------------------------------------
139
140 #define ENABLE_TIMER_INTERRUPT \
141 mtpcr x0,ASM_CR(PCR_CLR_IPI);\
142 mfpcr a0,ASM_CR(PCR_SR); \
143 li a1, SR_ET|SR_IM; \
144 or a0,a0,a1; \
145 mtpcr a0,ASM_CR(PCR_SR); \
146 la a0,_handler; \
147 mtpcr a0,ASM_CR(PCR_EVEC); \
148 mtpcr x0,ASM_CR(PCR_COUNT); \
149 addi a0,x0,60; \
150 mtpcr a0,ASM_CR(PCR_COMPARE);\
151
152 #define XCPT_HANDLER \
153 _handler: \
154 mtpcr a0,ASM_CR(PCR_K0); \
155 mtpcr a1,ASM_CR(PCR_K1); \
156 la a0,regspill; \
157 sd a2,0(a0); \
158 sd a3,8(a0); \
159 sd a4,16(a0); \
160 sd a5,24(a0); \
161 sd s0,32(a0); \
162 sd s1,40(a0); \
163 mfpcr s1,ASM_CR(PCR_VECBANK);\
164 mfpcr s0,ASM_CR(PCR_VECCFG); \
165 la a0,evac; \
166 vxcptevac a0; \
167 mtpcr s1,ASM_CR(PCR_VECBANK);\
168 srli a1,s0,12; \
169 andi a1,a1,0x3f; \
170 srli a2,s0,18; \
171 andi a2,a2,0x3f; \
172 vvcfg a1,a2; \
173 li a2,0xfff; \
174 and a1,s0,a2; \
175 vsetvl a1,a1; \
176 vxcpthold; \
177 li a5,0; \
178 _handler_loop: \
179 ld a1,0(a0); \
180 addi a0,a0,8; \
181 blt a1,x0,_done; \
182 srli a2,a1,32; \
183 andi a2,a2,0x1; \
184 beq a2,x0,_vcnt; \
185 _vcmd: \
186 beq a5,x0,_vcmd_skip; \
187 venqcmd a4,a3; \
188 _vcmd_skip: \
189 li a5,1; \
190 move a4,a1; \
191 srli a3,a4,36; \
192 andi a3,a3,0x1; \
193 _vimm1: \
194 srli a2,a4,35; \
195 andi a2,a2,0x1; \
196 beq a2,x0,_vimm2; \
197 ld a1,0(a0); \
198 addi a0,a0,8; \
199 venqimm1 a1,a3; \
200 _vimm2: \
201 srli a2,a4,34; \
202 andi a2,a2,0x1; \
203 beq a2,x0,_end; \
204 ld a1,0(a0); \
205 addi a0,a0,8; \
206 venqimm2 a1,a3; \
207 j _end; \
208 _vcnt: \
209 ld a2,0(a0); \
210 srli a2,a2,31; \
211 andi a2,a2,0x2; \
212 or a3,a3,a2; \
213 venqcnt a1,a3; \
214 _end: \
215 j _handler_loop; \
216 _done: \
217 beq a5,x0,_done_skip; \
218 venqcmd a4,a3; \
219 _done_skip: \
220 la a0,regspill; \
221 ld a2,0(a0); \
222 ld a3,8(a0); \
223 ld a4,16(a0); \
224 ld a5,24(a0); \
225 ld s0,32(a0); \
226 ld s1,40(a0); \
227 mfpcr a0,ASM_CR(PCR_COUNT); \
228 addi a0,a0,60; \
229 mtpcr a0,ASM_CR(PCR_COMPARE);\
230 mfpcr a0,ASM_CR(PCR_K0); \
231 mfpcr a1,ASM_CR(PCR_K1); \
232 eret; \
233
234 #endif