Don't emit vector instructions for now
[riscv-tests.git] / env / v / entry.S
1 #include "riscv_test.h"
2
3 #ifdef __riscv64
4 # define STORE sd
5 # define LOAD ld
6 # define REGBYTES 8
7 #else
8 # define STORE sw
9 # define LOAD lw
10 # define REGBYTES 4
11 #endif
12
13 .text
14 .global _start
15 _start:
16 la sp, stack_top
17 li a1, 1337
18 la a0, userstart
19 j vm_boot
20
21 save_tf: # write the trap frame onto the stack
22
23 # save gprs
24 STORE x3,3*REGBYTES(x2)
25 STORE x4,4*REGBYTES(x2)
26 STORE x5,5*REGBYTES(x2)
27 STORE x6,6*REGBYTES(x2)
28 STORE x7,7*REGBYTES(x2)
29 STORE x8,8*REGBYTES(x2)
30 STORE x9,9*REGBYTES(x2)
31 STORE x10,10*REGBYTES(x2)
32 STORE x11,11*REGBYTES(x2)
33 STORE x12,12*REGBYTES(x2)
34 STORE x13,13*REGBYTES(x2)
35 STORE x14,14*REGBYTES(x2)
36 STORE x15,15*REGBYTES(x2)
37 STORE x16,16*REGBYTES(x2)
38 STORE x17,17*REGBYTES(x2)
39 STORE x18,18*REGBYTES(x2)
40 STORE x19,19*REGBYTES(x2)
41 STORE x20,20*REGBYTES(x2)
42 STORE x21,21*REGBYTES(x2)
43 STORE x22,22*REGBYTES(x2)
44 STORE x23,23*REGBYTES(x2)
45 STORE x24,24*REGBYTES(x2)
46 STORE x25,25*REGBYTES(x2)
47 STORE x26,26*REGBYTES(x2)
48 STORE x27,27*REGBYTES(x2)
49 STORE x28,28*REGBYTES(x2)
50 STORE x29,29*REGBYTES(x2)
51 STORE x30,30*REGBYTES(x2)
52 STORE x31,31*REGBYTES(x2)
53
54 mfpcr x3,sup0
55 STORE x3,1*REGBYTES(x2) # x1 is in PCR_K0
56 mfpcr x3,sup1
57 STORE x3,2*REGBYTES(x2) # x2 is in PCR_K1
58
59 # get sr, epc, badvaddr, cause
60 mfpcr x3,status # sr
61 STORE x3,32*REGBYTES(x2)
62 mfpcr x4,epc # epc
63 STORE x4,33*REGBYTES(x2)
64 mfpcr x3,badvaddr # badvaddr
65 STORE x3,34*REGBYTES(x2)
66 mfpcr x3,cause # cause
67 STORE x3,35*REGBYTES(x2)
68
69 # get faulting insn, if it wasn't a fetch-related trap
70 li x5, CAUSE_MISALIGNED_FETCH
71 li x6, CAUSE_FAULT_FETCH
72 beq x3, x5, 1f
73 beq x3, x6, 1f
74 lh x3,0(x4)
75 lh x4,2(x4)
76 sh x3, 36*REGBYTES(x2)
77 sh x4,2+36*REGBYTES(x2)
78 1:
79
80 #mfpcr x3,ASM_CR(PCR_VECBANK) # vecbank
81 #STORE x3,37*REGBYTES(x2)
82 #mfpcr x3,ASM_CR(PCR_VECCFG) # veccfg
83 #STORE x3,38*REGBYTES(x2)
84
85 ret
86
87 .globl pop_tf
88 pop_tf: # write the trap frame onto the stack
89 # restore gprs
90 LOAD a1,32*REGBYTES(a0) # restore sr (should disable interrupts)
91 mtpcr a1,status
92
93 LOAD x1,1*REGBYTES(a0)
94 mtpcr x1,sup0
95 LOAD x1,2*REGBYTES(a0)
96 mtpcr x1,sup1
97 move x1,a0
98 LOAD x3,3*REGBYTES(x1)
99 LOAD x4,4*REGBYTES(x1)
100 LOAD x5,5*REGBYTES(x1)
101 LOAD x6,6*REGBYTES(x1)
102 LOAD x7,7*REGBYTES(x1)
103 LOAD x8,8*REGBYTES(x1)
104 LOAD x9,9*REGBYTES(x1)
105 LOAD x10,10*REGBYTES(x1)
106 LOAD x11,11*REGBYTES(x1)
107 LOAD x12,12*REGBYTES(x1)
108 LOAD x13,13*REGBYTES(x1)
109 LOAD x14,14*REGBYTES(x1)
110 LOAD x15,15*REGBYTES(x1)
111 LOAD x16,16*REGBYTES(x1)
112 LOAD x17,17*REGBYTES(x1)
113 LOAD x18,18*REGBYTES(x1)
114 LOAD x19,19*REGBYTES(x1)
115 LOAD x20,20*REGBYTES(x1)
116 LOAD x21,21*REGBYTES(x1)
117 LOAD x22,22*REGBYTES(x1)
118 LOAD x23,23*REGBYTES(x1)
119 LOAD x24,24*REGBYTES(x1)
120 LOAD x25,25*REGBYTES(x1)
121 LOAD x26,26*REGBYTES(x1)
122 LOAD x27,27*REGBYTES(x1)
123 LOAD x28,28*REGBYTES(x1)
124 LOAD x29,29*REGBYTES(x1)
125 LOAD x30,30*REGBYTES(x1)
126 LOAD x31,31*REGBYTES(x1)
127
128 # gtfo!
129 LOAD x2,33*REGBYTES(x1)
130 mtpcr x2,epc
131 mfpcr x1,sup0
132 mfpcr x2,sup1
133 eret
134
135 .global trap_entry
136 trap_entry:
137 mtpcr ra,sup0
138 mtpcr x2,sup1
139
140 # coming from kernel?
141 mfpcr ra,status
142 and ra,ra,SR_PS
143 bnez ra, 1f
144
145 # no, so start at the top of the stack
146 la x2,stack_top+MAX_TEST_PAGES*PGSIZE-SIZEOF_TRAPFRAME_T
147 jal save_tf
148 move sp,x2
149 setpcr status, SR_EI
150 move a0,x2
151 #if 0
152 mfpcr ra,status
153 and ra,ra,SR_EV
154 beqz ra, 2f
155 addi x2,x2,39*REGBYTES
156 vxcptsave x2
157 #endif
158 2:jal handle_trap
159
160 # when coming from kernel, continue below its stack
161 1:add x2, sp, -SIZEOF_TRAPFRAME_T
162 jal save_tf
163 move sp,x2
164 setpcr status, SR_EI
165 move a0,x2
166 jal handle_trap
167
168 .bss
169 .global stack_bot
170 .global stack_top
171 stack_bot:
172 .skip 32768
173 stack_top: