env/v/pcr.h

   1 #ifndef _RISCV_PCR_H
   2 #define _RISCV_PCR_H
   3
   4 #define SR_ET    0x00000001
   5 #define SR_EF    0x00000002
   6 #define SR_EV    0x00000004
   7 #define SR_EC    0x00000008
   8 #define SR_PS    0x00000010
   9 #define SR_S     0x00000020
  10 #define SR_U64   0x00000040
  11 #define SR_S64   0x00000080
  12 #define SR_VM    0x00000100
  13 #define SR_IM    0x00FF0000
  14 #define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM)
  15 #define SR_IM_SHIFT 16
  16
  17 #define PCR_SR       0
  18 #define PCR_EPC      1
  19 #define PCR_BADVADDR 2
  20 #define PCR_EVEC     3
  21 #define PCR_COUNT    4
  22 #define PCR_COMPARE  5
  23 #define PCR_CAUSE    6
  24 #define PCR_PTBR     7
  25 #define PCR_SEND_IPI 8
  26 #define PCR_CLR_IPI  9
  27 #define PCR_COREID   10
  28 #define PCR_IMPL     11
  29 #define PCR_K0       12
  30 #define PCR_K1       13
  31 #define PCR_VECBANK  18
  32 #define PCR_VECCFG   19
  33 #define PCR_RESET    29
  34 #define PCR_TOHOST   30
  35 #define PCR_FROMHOST 31
  36
  37 #define IMPL_ISASIM 1
  38 #define IMPL_ROCKET 2
  39
  40 #define IRQ_IPI   5
  41 #define IRQ_TIMER 7
  42
  43 #define CAUSE_MISALIGNED_FETCH 0
  44 #define CAUSE_FAULT_FETCH 1
  45 #define CAUSE_ILLEGAL_INSTRUCTION 2
  46 #define CAUSE_PRIVILEGED_INSTRUCTION 3
  47 #define CAUSE_FP_DISABLED 4
  48 #define CAUSE_SYSCALL 6
  49 #define CAUSE_BREAKPOINT 7
  50 #define CAUSE_MISALIGNED_LOAD 8
  51 #define CAUSE_MISALIGNED_STORE 9
  52 #define CAUSE_FAULT_LOAD 10
  53 #define CAUSE_FAULT_STORE 11
  54 #define CAUSE_VECTOR_DISABLED 12
  55 #define CAUSE_VECTOR_BANK 13
  56
  57 #define CAUSE_VECTOR_MISALIGNED_FETCH 24
  58 #define CAUSE_VECTOR_FAULT_FETCH 25
  59 #define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26
  60 #define CAUSE_VECTOR_ILLEGAL_COMMAND 27
  61 #define CAUSE_VECTOR_MISALIGNED_LOAD 28
  62 #define CAUSE_VECTOR_MISALIGNED_STORE 29
  63 #define CAUSE_VECTOR_FAULT_LOAD 30
  64 #define CAUSE_VECTOR_FAULT_STORE 31
  65
  66 #ifdef __riscv
  67
  68 #define ASM_CR(r)   _ASM_CR(r)
  69 #define _ASM_CR(r)  cr##r
  70
  71 #ifndef __ASSEMBLER__
  72
  73 #define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
  74           asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
  75           __tmp2; })
  76
  77 #define mfpcr(reg) ({ long __tmp; \
  78           asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
  79           __tmp; })
  80
  81 #define setpcr(reg,val) ({ long __tmp; \
  82           asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
  83           __tmp; })
  84
  85 #define clearpcr(reg,val) ({ long __tmp; \
  86           asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
  87           __tmp; })
  88
  89 #endif
  90
  91 #endif
  92
  93 #endif