env/v/riscv_test.h

   1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
   2 #define _ENV_VIRTUAL_SINGLE_CORE_H
   3
   4 //-----------------------------------------------------------------------
   5 // Begin Macro
   6 //-----------------------------------------------------------------------
   7
   8 #define RVTEST_RV64U                                                    \
   9   .macro init;                                                          \
  10   .endm
  11
  12 #define RVTEST_RV64UF                                                   \
  13   .macro init;                                                          \
  14   fssr x0;                                                              \
  15   .endm
  16
  17 #define RVTEST_RV64UV                                                   \
  18         RVTEST_RV64UF
  19
  20 #define RVTEST_CODE_BEGIN                                               \
  21         .text;                                                          \
  22         .align  13;                                                     \
  23         .global userstart;                                              \
  24 userstart:                                                              \
  25         init
  26
  27 //-----------------------------------------------------------------------
  28 // End Macro
  29 //-----------------------------------------------------------------------
  30
  31 #define RVTEST_CODE_END                                                 \
  32
  33 //-----------------------------------------------------------------------
  34 // Pass/Fail Macro
  35 //-----------------------------------------------------------------------
  36
  37 #define RVTEST_PASS li a0, 1; syscall;
  38 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
  39
  40 //-----------------------------------------------------------------------
  41 // Data Section Macro
  42 //-----------------------------------------------------------------------
  43
  44 #define RVTEST_DATA_BEGIN
  45 #define RVTEST_DATA_END
  46
  47 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
  48 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
  49
  50 //-----------------------------------------------------------------------
  51 // Supervisor mode definitions and macros
  52 //-----------------------------------------------------------------------
  53
  54 #include "../pcr.h"
  55 #include "../hwacha_xcpt.h"
  56
  57 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
  58 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
  59 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
  60 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
  61 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
  62
  63 #define fence() ({ \
  64           asm volatile ("fence" ::: "memory"); })
  65
  66 #define vxcptkill() ({ \
  67           asm volatile ("vxcptkill"); })
  68
  69 #define vxcpthold() ({ \
  70           asm volatile ("vxcpthold"); })
  71
  72 #define venqcmd(bits, pf) ({ \
  73           asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
  74
  75 #define venqimm1(bits, pf) ({ \
  76           asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
  77
  78 #define venqimm2(bits, pf) ({ \
  79           asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
  80
  81 #define venqcnt(bits, pf) ({ \
  82           asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
  83
  84 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
  85 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
  86
  87 #define PGSHIFT 13
  88 #define PGSIZE (1 << PGSHIFT)
  89
  90 #define SIZEOF_TRAPFRAME_T 20784
  91
  92 #ifndef __ASSEMBLER__
  93
  94 static inline void vsetcfg(long cfg)
  95 {
  96   asm volatile ("vsetcfg %0" : : "r"(cfg));
  97 }
  98
  99 static inline void vsetvl(long vl)
 100 {
 101   long __tmp;
 102   asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl));
 103 }
 104
 105 static inline long vgetcfg()
 106 {
 107   int cfg;
 108   asm volatile ("vgetcfg %0" : "=r"(cfg) :);
 109   return cfg;
 110 }
 111
 112 static inline long vgetvl()
 113 {
 114   int vl;
 115   asm volatile ("vgetvl %0" : "=r"(vl) :);
 116 }
 117
 118 static inline long vxcptaux()
 119 {
 120   int aux;
 121   asm volatile ("vxcptaux %0" : "=r"(aux) :);
 122   return aux;
 123 }
 124
 125 static inline void vxcptrestore(long* mem)
 126 {
 127   asm volatile("vxcptrestore %0" : : "r"(mem) : "memory");
 128 }
 129
 130 static inline void vxcptevac(long* mem)
 131 {
 132   asm volatile ("vxcptevac %0" : : "r"(mem));
 133 }
 134
 135 typedef unsigned long pte_t;
 136 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
 137 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
 138 #define VPN_BITS (PTIDXBITS * LEVELS)
 139 #define VA_BITS (VPN_BITS + PGSHIFT)
 140 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))
 141
 142 typedef struct
 143 {
 144   long gpr[32];
 145   long sr;
 146   long epc;
 147   long badvaddr;
 148   long cause;
 149   long insn;
 150   long hwacha_cause;
 151   long evac[2560];
 152 } trapframe_t;
 153 #endif
 154
 155 #endif