2a1710d51ad8e341dc809147678047fa50b69b48
[riscv-tests.git] / env / v / riscv_test.h
1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
2 #define _ENV_VIRTUAL_SINGLE_CORE_H
3
4 //-----------------------------------------------------------------------
5 // Begin Macro
6 //-----------------------------------------------------------------------
7
8 #define RVTEST_RV64U \
9
10 #define RVTEST_RV64S \
11
12 #define RVTEST_FP_ENABLE \
13 mtfsr x0; \
14
15 #define RVTEST_VEC_ENABLE \
16 mfpcr t0, cr0; \
17 ori t0, t0, 4; \
18 mtpcr t0, cr0; \
19 li t0, 0xff; \
20 mtpcr t0, cr11; \
21
22 #define RVTEST_CODE_BEGIN \
23 .text; \
24 .align 13; \
25 .global userstart; \
26 userstart: \
27 RVTEST_FP_ENABLE; \
28
29 //-----------------------------------------------------------------------
30 // End Macro
31 //-----------------------------------------------------------------------
32
33 #define RVTEST_CODE_END \
34
35 //-----------------------------------------------------------------------
36 // Pass/Fail Macro
37 //-----------------------------------------------------------------------
38
39 #define RVTEST_PASS li a0, 1; syscall;
40 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
41
42 //-----------------------------------------------------------------------
43 // Data Section Macro
44 //-----------------------------------------------------------------------
45
46 #define RVTEST_DATA_BEGIN
47 #define RVTEST_DATA_END
48
49 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
50 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
51
52 //-----------------------------------------------------------------------
53 // Supervisor mode definitions and macros
54 //-----------------------------------------------------------------------
55
56 #include "pcr.h"
57
58 #define vvcfg(nxregs, nfregs) ({ \
59 asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); })
60
61 #define vsetvl(vl) ({ long __tmp; \
62 asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl)); })
63
64 #define vcfg(word) ({ vvcfg((word)>>12, (word)>>18); vsetvl((word)); })
65
66 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
67 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
68 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
69 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
70 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
71
72 #define fencevl() ({ \
73 asm volatile ("fence.v.l" ::: "memory"); })
74
75 #define vxcptkill() ({ \
76 asm volatile ("vxcptkill"); })
77
78 #define vxcpthold() ({ \
79 asm volatile ("vxcpthold"); })
80
81 #define venqcmd(bits, pf) ({ \
82 asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
83
84 #define venqimm1(bits, pf) ({ \
85 asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
86
87 #define venqimm2(bits, pf) ({ \
88 asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
89
90 #define venqcnt(bits, pf) ({ \
91 asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
92
93 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
94 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
95
96 #define PGSHIFT 13
97 #define PGSIZE (1 << PGSHIFT)
98
99 #define SIZEOF_TRAPFRAME_T 1336
100
101 #ifndef __ASSEMBLER__
102
103
104 typedef unsigned long pte_t;
105 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
106 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
107 #define VPN_BITS (PTIDXBITS * LEVELS)
108 #define VA_BITS (VPN_BITS + PGSHIFT)
109 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))
110
111 typedef struct
112 {
113 long gpr[32];
114 long sr;
115 long epc;
116 long badvaddr;
117 long cause;
118 long insn;
119 long vecbank;
120 long veccfg;
121 long evac[128];
122 } trapframe_t;
123 #endif
124
125 #endif