env/v/riscv_test.h

   1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
   2 #define _ENV_VIRTUAL_SINGLE_CORE_H
   3
   4 //-----------------------------------------------------------------------
   5 // Begin Macro
   6 //-----------------------------------------------------------------------
   7
   8 #define RVTEST_RV64U                                                    \
   9   .text;                                                                \
  10 init:                                                                   \
  11   ret
  12
  13 #define RVTEST_RV64UF                                                   \
  14   .text;                                                                \
  15 init:                                                                   \
  16   mtfsr x0;                                                             \
  17   ret
  18
  19 #define RVTEST_RV64S                                                    \
  20
  21 #define RVTEST_VEC_ENABLE                                               \
  22   mfpcr t0, cr0;                                                        \
  23   ori   t0, t0, 4;                                                      \
  24   mtpcr t0, cr0;                                                        \
  25   li    t0, 0xff;                                                       \
  26   mtpcr t0, cr11;                                                       \
  27
  28 #define RVTEST_CODE_BEGIN                                               \
  29         .text;                                                          \
  30         .align  13;                                                     \
  31         .global userstart;                                              \
  32 userstart:                                                              \
  33         jal init
  34
  35 //-----------------------------------------------------------------------
  36 // End Macro
  37 //-----------------------------------------------------------------------
  38
  39 #define RVTEST_CODE_END                                                 \
  40
  41 //-----------------------------------------------------------------------
  42 // Pass/Fail Macro
  43 //-----------------------------------------------------------------------
  44
  45 #define RVTEST_PASS li a0, 1; syscall;
  46 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
  47
  48 //-----------------------------------------------------------------------
  49 // Data Section Macro
  50 //-----------------------------------------------------------------------
  51
  52 #define RVTEST_DATA_BEGIN
  53 #define RVTEST_DATA_END
  54
  55 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
  56 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
  57
  58 //-----------------------------------------------------------------------
  59 // Supervisor mode definitions and macros
  60 //-----------------------------------------------------------------------
  61
  62 #include "pcr.h"
  63
  64 #define vvcfg(nxregs, nfregs) ({ \
  65           asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); })
  66
  67 #define vsetvl(vl) ({ long __tmp; \
  68           asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl)); })
  69
  70 #define vcfg(word) ({ vvcfg((word)>>12, (word)>>18); vsetvl((word)); })
  71
  72 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
  73 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
  74 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
  75 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
  76 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
  77
  78 #define fencevl() ({ \
  79           asm volatile ("fence.v.l" ::: "memory"); })
  80
  81 #define vxcptkill() ({ \
  82           asm volatile ("vxcptkill"); })
  83
  84 #define vxcpthold() ({ \
  85           asm volatile ("vxcpthold"); })
  86
  87 #define venqcmd(bits, pf) ({ \
  88           asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
  89
  90 #define venqimm1(bits, pf) ({ \
  91           asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
  92
  93 #define venqimm2(bits, pf) ({ \
  94           asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
  95
  96 #define venqcnt(bits, pf) ({ \
  97           asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
  98
  99 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
 100 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
 101
 102 #define PGSHIFT 13
 103 #define PGSIZE (1 << PGSHIFT)
 104
 105 #define SIZEOF_TRAPFRAME_T 1336
 106
 107 #ifndef __ASSEMBLER__
 108
 109
 110 typedef unsigned long pte_t;
 111 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
 112 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
 113 #define VPN_BITS (PTIDXBITS * LEVELS)
 114 #define VA_BITS (VPN_BITS + PGSHIFT)
 115 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))
 116
 117 typedef struct
 118 {
 119   long gpr[32];
 120   long sr;
 121   long epc;
 122   long badvaddr;
 123   long cause;
 124   long insn;
 125   long vecbank;
 126   long veccfg;
 127   long evac[128];
 128 } trapframe_t;
 129 #endif
 130
 131 #endif