1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
2 #define _ENV_VIRTUAL_SINGLE_CORE_H
4 //-----------------------------------------------------------------------
6 //-----------------------------------------------------------------------
13 #define RVTEST_RV64UF \
19 #define RVTEST_RV64S \
21 #define RVTEST_VEC_ENABLE \
28 #define RVTEST_CODE_BEGIN \
35 //-----------------------------------------------------------------------
37 //-----------------------------------------------------------------------
39 #define RVTEST_CODE_END \
41 //-----------------------------------------------------------------------
43 //-----------------------------------------------------------------------
45 #define RVTEST_PASS li a0, 1; syscall;
46 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
48 //-----------------------------------------------------------------------
50 //-----------------------------------------------------------------------
52 #define RVTEST_DATA_BEGIN
53 #define RVTEST_DATA_END
55 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
56 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
58 //-----------------------------------------------------------------------
59 // Supervisor mode definitions and macros
60 //-----------------------------------------------------------------------
64 #define vvcfg(nxregs, nfregs) ({ \
65 asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); })
67 #define vsetvl(vl) ({ long __tmp; \
68 asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl)); })
70 #define vcfg(word) ({ vvcfg((word)>>12, (word)>>18); vsetvl((word)); })
72 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
73 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
74 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
75 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
76 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
78 #define fencevl() ({ \
79 asm volatile ("fence.v.l" ::: "memory"); })
81 #define vxcptkill() ({ \
82 asm volatile ("vxcptkill"); })
84 #define vxcpthold() ({ \
85 asm volatile ("vxcpthold"); })
87 #define venqcmd(bits, pf) ({ \
88 asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
90 #define venqimm1(bits, pf) ({ \
91 asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
93 #define venqimm2(bits, pf) ({ \
94 asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
96 #define venqcnt(bits, pf) ({ \
97 asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
99 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
100 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
103 #define PGSIZE (1 << PGSHIFT)
105 #define SIZEOF_TRAPFRAME_T 1336
107 #ifndef __ASSEMBLER__
110 typedef unsigned long pte_t
;
111 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
112 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
113 #define VPN_BITS (PTIDXBITS * LEVELS)
114 #define VA_BITS (VPN_BITS + PGSHIFT)
115 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))