env/v/riscv_test.h

   1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
   2 #define _ENV_VIRTUAL_SINGLE_CORE_H
   3
   4 //-----------------------------------------------------------------------
   5 // Begin Macro
   6 //-----------------------------------------------------------------------
   7
   8 #define RVTEST_RV64U                                                    \
   9   .macro init;                                                          \
  10   .endm
  11
  12 #define RVTEST_RV64UF                                                   \
  13   .macro init;                                                          \
  14   fssr x0;                                                              \
  15   .endm
  16
  17 #define RVTEST_VEC_ENABLE                                               \
  18
  19 #define RVTEST_CODE_BEGIN                                               \
  20         .text;                                                          \
  21         .align  13;                                                     \
  22         .global userstart;                                              \
  23 userstart:                                                              \
  24         init
  25
  26 //-----------------------------------------------------------------------
  27 // End Macro
  28 //-----------------------------------------------------------------------
  29
  30 #define RVTEST_CODE_END                                                 \
  31
  32 //-----------------------------------------------------------------------
  33 // Pass/Fail Macro
  34 //-----------------------------------------------------------------------
  35
  36 #define RVTEST_PASS li a0, 1; syscall;
  37 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
  38
  39 //-----------------------------------------------------------------------
  40 // Data Section Macro
  41 //-----------------------------------------------------------------------
  42
  43 #define RVTEST_DATA_BEGIN
  44 #define RVTEST_DATA_END
  45
  46 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
  47 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
  48
  49 //-----------------------------------------------------------------------
  50 // Supervisor mode definitions and macros
  51 //-----------------------------------------------------------------------
  52
  53 #include "../pcr.h"
  54 #include "../hwacha_xcpt.h"
  55
  56 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
  57 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
  58 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
  59 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
  60 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
  61
  62 #define fence() ({ \
  63           asm volatile ("fence" ::: "memory"); })
  64
  65 #define vxcptkill() ({ \
  66           asm volatile ("vxcptkill"); })
  67
  68 #define vxcpthold() ({ \
  69           asm volatile ("vxcpthold"); })
  70
  71 #define venqcmd(bits, pf) ({ \
  72           asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
  73
  74 #define venqimm1(bits, pf) ({ \
  75           asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
  76
  77 #define venqimm2(bits, pf) ({ \
  78           asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
  79
  80 #define venqcnt(bits, pf) ({ \
  81           asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
  82
  83 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
  84 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
  85
  86 #define PGSHIFT 13
  87 #define PGSIZE (1 << PGSHIFT)
  88
  89 #define SIZEOF_TRAPFRAME_T 1328
  90
  91 #ifndef __ASSEMBLER__
  92
  93 static inline void vsetcfg(long cfg)
  94 {
  95   asm volatile ("vsetcfg %0" : : "r"(cfg));
  96 }
  97
  98 static inline void vsetvl(long vl)
  99 {
 100   long __tmp;
 101   asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl));
 102 }
 103
 104 static inline long vgetcfg()
 105 {
 106   int cfg;
 107   asm volatile ("vgetcfg %0" : "=r"(cfg) :);
 108   return cfg;
 109 }
 110
 111 static inline long vgetvl()
 112 {
 113   int vl;
 114   asm volatile ("vgetvl %0" : "=r"(vl) :);
 115 }
 116
 117 static inline long vxcptaux()
 118 {
 119   int aux;
 120   asm volatile ("vxcptaux %0" : "=r"(aux) :);
 121   return aux;
 122 }
 123
 124 static inline void vxcptrestore(long* mem)
 125 {
 126   asm volatile("vxcptrestore %0" : : "r"(mem) : "memory");
 127 }
 128
 129 static inline void vxcptevac(long* mem)
 130 {
 131   asm volatile ("vxcptevac %0" : : "r"(mem));
 132 }
 133
 134 typedef unsigned long pte_t;
 135 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
 136 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
 137 #define VPN_BITS (PTIDXBITS * LEVELS)
 138 #define VA_BITS (VPN_BITS + PGSHIFT)
 139 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))
 140
 141 typedef struct
 142 {
 143   long gpr[32];
 144   long sr;
 145   long epc;
 146   long badvaddr;
 147   long cause;
 148   long insn;
 149   long hwacha_cause;
 150   long evac[128];
 151 } trapframe_t;
 152 #endif
 153
 154 #endif