1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
2 #define _ENV_VIRTUAL_SINGLE_CORE_H
4 //-----------------------------------------------------------------------
6 //-----------------------------------------------------------------------
12 #define RVTEST_RV64UF \
17 #define RVTEST_VEC_ENABLE \
19 #define RVTEST_CODE_BEGIN \
26 //-----------------------------------------------------------------------
28 //-----------------------------------------------------------------------
30 #define RVTEST_CODE_END \
32 //-----------------------------------------------------------------------
34 //-----------------------------------------------------------------------
36 #define RVTEST_PASS li a0, 1; syscall;
37 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
39 //-----------------------------------------------------------------------
41 //-----------------------------------------------------------------------
43 #define RVTEST_DATA_BEGIN
44 #define RVTEST_DATA_END
46 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
47 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
49 //-----------------------------------------------------------------------
50 // Supervisor mode definitions and macros
51 //-----------------------------------------------------------------------
54 #include "../hwacha_xcpt.h"
56 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
57 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
58 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
59 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
60 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
63 asm volatile ("fence" ::: "memory"); })
65 #define vxcptkill() ({ \
66 asm volatile ("vxcptkill"); })
68 #define vxcpthold() ({ \
69 asm volatile ("vxcpthold"); })
71 #define venqcmd(bits, pf) ({ \
72 asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
74 #define venqimm1(bits, pf) ({ \
75 asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
77 #define venqimm2(bits, pf) ({ \
78 asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
80 #define venqcnt(bits, pf) ({ \
81 asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
83 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
84 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
87 #define PGSIZE (1 << PGSHIFT)
89 #define SIZEOF_TRAPFRAME_T 20784
93 static inline void vsetcfg(long cfg
)
95 asm volatile ("vsetcfg %0" : : "r"(cfg
));
98 static inline void vsetvl(long vl
)
101 asm volatile ("vsetvl %0,%1" : "=r"(__tmp
) : "r"(vl
));
104 static inline long vgetcfg()
107 asm volatile ("vgetcfg %0" : "=r"(cfg
) :);
111 static inline long vgetvl()
114 asm volatile ("vgetvl %0" : "=r"(vl
) :);
117 static inline long vxcptaux()
120 asm volatile ("vxcptaux %0" : "=r"(aux
) :);
124 static inline void vxcptrestore(long* mem
)
126 asm volatile("vxcptrestore %0" : : "r"(mem
) : "memory");
129 static inline void vxcptevac(long* mem
)
131 asm volatile ("vxcptevac %0" : : "r"(mem
));
134 typedef unsigned long pte_t
;
135 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
136 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
137 #define VPN_BITS (PTIDXBITS * LEVELS)
138 #define VA_BITS (VPN_BITS + PGSHIFT)
139 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))