e37ec05b7c1cdaff779dd71fdc1b706ae897c2d2
[riscv-tests.git] / env / v / riscv_test.h
1 #ifndef _ENV_VIRTUAL_SINGLE_CORE_H
2 #define _ENV_VIRTUAL_SINGLE_CORE_H
3
4 //-----------------------------------------------------------------------
5 // Begin Macro
6 //-----------------------------------------------------------------------
7
8 #define RVTEST_RV64U \
9
10 #define RVTEST_RV64S \
11
12 #define RVTEST_FP_ENABLE \
13 mfpcr t0, cr0; \
14 or t0, t0, 2; \
15 mtpcr t0, cr0; \
16 mtfsr x0; \
17
18 #define RVTEST_VEC_ENABLE \
19 mfpcr t0, cr0; \
20 ori t0, t0, 4; \
21 mtpcr t0, cr0; \
22 li t0, 0xff; \
23 mtpcr t0, cr11; \
24
25 #define RVTEST_CODE_BEGIN \
26 .text; \
27 .align 13; \
28 .global userstart; \
29 userstart: \
30
31 //-----------------------------------------------------------------------
32 // End Macro
33 //-----------------------------------------------------------------------
34
35 #define RVTEST_CODE_END \
36
37 //-----------------------------------------------------------------------
38 // Pass/Fail Macro
39 //-----------------------------------------------------------------------
40
41 #define RVTEST_PASS li a0, 1; syscall;
42 #define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
43
44 //-----------------------------------------------------------------------
45 // Data Section Macro
46 //-----------------------------------------------------------------------
47
48 #define RVTEST_DATA_BEGIN
49 #define RVTEST_DATA_END
50
51 //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature:
52 //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
53
54 //-----------------------------------------------------------------------
55 // Supervisor mode definitions and macros
56 //-----------------------------------------------------------------------
57
58 #include "pcr.h"
59
60 #define vvcfg(nxregs, nfregs) ({ \
61 asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); })
62
63 #define vsetvl(vl) ({ long __tmp; \
64 asm volatile ("vsetvl %0,%1" : "=r"(__tmp) : "r"(vl)); })
65
66 #define vcfg(word) ({ vvcfg((word)>>12, (word)>>18); vsetvl((word)); })
67
68 #define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
69 #define dword_bit_cnt(dw) (!dword_bit_cmd(dw))
70 #define dword_bit_imm1(dw) ((dw >> 35) & 0x1)
71 #define dword_bit_imm2(dw) ((dw >> 34) & 0x1)
72 #define dword_bit_pf(dw) ((dw >> 36) & 0x1)
73
74 #define fencevl() ({ \
75 asm volatile ("fence.v.l" ::: "memory"); })
76
77 #define vxcptkill() ({ \
78 asm volatile ("vxcptkill"); })
79
80 #define vxcpthold() ({ \
81 asm volatile ("vxcpthold"); })
82
83 #define venqcmd(bits, pf) ({ \
84 asm volatile ("venqcmd %0,%1" : : "r"(bits), "r"(pf)); })
85
86 #define venqimm1(bits, pf) ({ \
87 asm volatile ("venqimm1 %0,%1" : : "r"(bits), "r"(pf)); })
88
89 #define venqimm2(bits, pf) ({ \
90 asm volatile ("venqimm2 %0,%1" : : "r"(bits), "r"(pf)); })
91
92 #define venqcnt(bits, pf) ({ \
93 asm volatile ("venqcnt %0,%1" :: "r"(bits), "r"(pf)); })
94
95 #define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
96 #define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
97
98 #define PGSHIFT 13
99 #define PGSIZE (1 << PGSHIFT)
100
101 #define SIZEOF_TRAPFRAME_T 1336
102
103 #ifndef __ASSEMBLER__
104
105
106 typedef unsigned long pte_t;
107 #define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
108 #define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
109 #define VPN_BITS (PTIDXBITS * LEVELS)
110 #define VA_BITS (VPN_BITS + PGSHIFT)
111 #define PTES_PER_PT (PGSIZE/sizeof(pte_t))
112
113 typedef struct
114 {
115 long gpr[32];
116 long sr;
117 long epc;
118 long badvaddr;
119 long cause;
120 long insn;
121 long vecbank;
122 long veccfg;
123 long evac[128];
124 } trapframe_t;
125 #endif
126
127 #endif