isa/macros/scalar/test_macros.h

   1 #ifndef __TEST_MACROS_SCALAR_H
   2 #define __TEST_MACROS_SCALAR_H
   3
   4
   5 #-----------------------------------------------------------------------
   6 # Helper macros
   7 #-----------------------------------------------------------------------
   8
   9 #define TEST_CASE( testnum, testreg, correctval, code... ) \
  10 test_ ## testnum: \
  11     code; \
  12     li  x29, correctval; \
  13     li  TESTNUM, testnum; \
  14     bne testreg, x29, fail;
  15
  16 #define TEST_CASE_JUMP( testnum, testreg, correctval, code... ) \
  17 test_ ## testnum: \
  18     code; \
  19     li  x29, correctval; \
  20     li  TESTNUM, testnum; \
  21     beq testreg, x29, pass_ ## testnum; \
  22     j fail; \
  23 pass_ ## testnum: \
  24
  25 # We use a macro hack to simpify code generation for various numbers
  26 # of bubble cycles.
  27
  28 #define TEST_INSERT_NOPS_0
  29 #define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
  30 #define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
  31 #define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
  32 #define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
  33 #define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
  34 #define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
  35 #define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
  36 #define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
  37 #define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
  38 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
  39
  40
  41 #-----------------------------------------------------------------------
  42 # RV64UI MACROS
  43 #-----------------------------------------------------------------------
  44
  45 #-----------------------------------------------------------------------
  46 # Tests for instructions with immediate operand
  47 #-----------------------------------------------------------------------
  48
  49 #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
  50
  51 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
  52     TEST_CASE( testnum, x3, result, \
  53       li  x1, val1; \
  54       inst x3, x1, SEXT_IMM(imm); \
  55     )
  56
  57 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
  58     TEST_CASE( testnum, x1, result, \
  59       li  x1, val1; \
  60       inst x1, x1, SEXT_IMM(imm); \
  61     )
  62
  63 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  64     TEST_CASE( testnum, x6, result, \
  65       li  x4, 0; \
  66 1:    li  x1, val1; \
  67       inst x3, x1, SEXT_IMM(imm); \
  68       TEST_INSERT_NOPS_ ## nop_cycles \
  69       addi  x6, x3, 0; \
  70       addi  x4, x4, 1; \
  71       li  x5, 2; \
  72       bne x4, x5, 1b \
  73     )
  74
  75 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  76     TEST_CASE( testnum, x3, result, \
  77       li  x4, 0; \
  78 1:    li  x1, val1; \
  79       TEST_INSERT_NOPS_ ## nop_cycles \
  80       inst x3, x1, SEXT_IMM(imm); \
  81       addi  x4, x4, 1; \
  82       li  x5, 2; \
  83       bne x4, x5, 1b \
  84     )
  85
  86 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
  87     TEST_CASE( testnum, x1, result, \
  88       inst x1, x0, SEXT_IMM(imm); \
  89     )
  90
  91 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
  92     TEST_CASE( testnum, x0, 0, \
  93       li  x1, val1; \
  94       inst x0, x1, SEXT_IMM(imm); \
  95     )
  96
  97 #-----------------------------------------------------------------------
  98 # Tests for vector config instructions
  99 #-----------------------------------------------------------------------
 100
 101 #define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
 102     TEST_CASE_JUMP( testnum, x1, result, \
 103       li x1, (bank << 12); \
 104       vsetcfg x1,nxpr,nfpr; \
 105       li x1, vl; \
 106       vsetvl x1,x1; \
 107     )
 108
 109 #define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
 110     TEST_CASE_JUMP( testnum, x1, result, \
 111       li x1, (bank << 12) | (nfpr << 6) | nxpr; \
 112       vsetcfg x1; \
 113       li x1, vl; \
 114       vsetvl x1,x1; \
 115     )
 116
 117 #define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
 118     TEST_CASE_JUMP( testnum, x1, result, \
 119       li x1, (bank << 12); \
 120       vsetcfg x1,nxpr,nfpr; \
 121       li x1, vl; \
 122       vsetvl x1, x1; \
 123     )
 124
 125 #-----------------------------------------------------------------------
 126 # Tests for an instruction with register operands
 127 #-----------------------------------------------------------------------
 128
 129 #define TEST_R_OP( testnum, inst, result, val1 ) \
 130     TEST_CASE( testnum, x3, result, \
 131       li  x1, val1; \
 132       inst x3, x1; \
 133     )
 134
 135 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
 136     TEST_CASE( testnum, x1, result, \
 137       li  x1, val1; \
 138       inst x1, x1; \
 139     )
 140
 141 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
 142     TEST_CASE( testnum, x6, result, \
 143       li  x4, 0; \
 144 1:    li  x1, val1; \
 145       inst x3, x1; \
 146       TEST_INSERT_NOPS_ ## nop_cycles \
 147       addi  x6, x3, 0; \
 148       addi  x4, x4, 1; \
 149       li  x5, 2; \
 150       bne x4, x5, 1b \
 151     )
 152
 153 #-----------------------------------------------------------------------
 154 # Tests for an instruction with register-register operands
 155 #-----------------------------------------------------------------------
 156
 157 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
 158     TEST_CASE( testnum, x3, result, \
 159       li  x1, val1; \
 160       li  x2, val2; \
 161       inst x3, x1, x2; \
 162     )
 163
 164 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
 165     TEST_CASE( testnum, x1, result, \
 166       li  x1, val1; \
 167       li  x2, val2; \
 168       inst x1, x1, x2; \
 169     )
 170
 171 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
 172     TEST_CASE( testnum, x2, result, \
 173       li  x1, val1; \
 174       li  x2, val2; \
 175       inst x2, x1, x2; \
 176     )
 177
 178 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
 179     TEST_CASE( testnum, x1, result, \
 180       li  x1, val1; \
 181       inst x1, x1, x1; \
 182     )
 183
 184 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
 185     TEST_CASE( testnum, x6, result, \
 186       li  x4, 0; \
 187 1:    li  x1, val1; \
 188       li  x2, val2; \
 189       inst x3, x1, x2; \
 190       TEST_INSERT_NOPS_ ## nop_cycles \
 191       addi  x6, x3, 0; \
 192       addi  x4, x4, 1; \
 193       li  x5, 2; \
 194       bne x4, x5, 1b \
 195     )
 196
 197 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 198     TEST_CASE( testnum, x3, result, \
 199       li  x4, 0; \
 200 1:    li  x1, val1; \
 201       TEST_INSERT_NOPS_ ## src1_nops \
 202       li  x2, val2; \
 203       TEST_INSERT_NOPS_ ## src2_nops \
 204       inst x3, x1, x2; \
 205       addi  x4, x4, 1; \
 206       li  x5, 2; \
 207       bne x4, x5, 1b \
 208     )
 209
 210 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 211     TEST_CASE( testnum, x3, result, \
 212       li  x4, 0; \
 213 1:    li  x2, val2; \
 214       TEST_INSERT_NOPS_ ## src1_nops \
 215       li  x1, val1; \
 216       TEST_INSERT_NOPS_ ## src2_nops \
 217       inst x3, x1, x2; \
 218       addi  x4, x4, 1; \
 219       li  x5, 2; \
 220       bne x4, x5, 1b \
 221     )
 222
 223 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
 224     TEST_CASE( testnum, x2, result, \
 225       li x1, val; \
 226       inst x2, x0, x1; \
 227     )
 228
 229 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
 230     TEST_CASE( testnum, x2, result, \
 231       li x1, val; \
 232       inst x2, x1, x0; \
 233     )
 234
 235 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
 236     TEST_CASE( testnum, x1, result, \
 237       inst x1, x0, x0; \
 238     )
 239
 240 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
 241     TEST_CASE( testnum, x0, 0, \
 242       li x1, val1; \
 243       li x2, val2; \
 244       inst x0, x1, x2; \
 245     )
 246
 247 #-----------------------------------------------------------------------
 248 # Test memory instructions
 249 #-----------------------------------------------------------------------
 250
 251 #define TEST_LD_OP( testnum, inst, result, offset, base ) \
 252     TEST_CASE( testnum, x3, result, \
 253       la  x1, base; \
 254       inst x3, offset(x1); \
 255     )
 256
 257 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
 258     TEST_CASE( testnum, x3, result, \
 259       la  x1, base; \
 260       li  x2, result; \
 261       store_inst x2, offset(x1); \
 262       load_inst x3, offset(x1); \
 263     )
 264
 265 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 266 test_ ## testnum: \
 267     li  TESTNUM, testnum; \
 268     li  x4, 0; \
 269 1:  la  x1, base; \
 270     inst x3, offset(x1); \
 271     TEST_INSERT_NOPS_ ## nop_cycles \
 272     addi  x6, x3, 0; \
 273     li  x29, result; \
 274     bne x6, x29, fail; \
 275     addi  x4, x4, 1; \
 276     li  x5, 2; \
 277     bne x4, x5, 1b; \
 278
 279 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 280 test_ ## testnum: \
 281     li  TESTNUM, testnum; \
 282     li  x4, 0; \
 283 1:  la  x1, base; \
 284     TEST_INSERT_NOPS_ ## nop_cycles \
 285     inst x3, offset(x1); \
 286     li  x29, result; \
 287     bne x3, x29, fail; \
 288     addi  x4, x4, 1; \
 289     li  x5, 2; \
 290     bne x4, x5, 1b \
 291
 292 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 293 test_ ## testnum: \
 294     li  TESTNUM, testnum; \
 295     li  x4, 0; \
 296 1:  la  x1, result; \
 297     TEST_INSERT_NOPS_ ## src1_nops \
 298     la  x2, base; \
 299     TEST_INSERT_NOPS_ ## src2_nops \
 300     store_inst x1, offset(x2); \
 301     load_inst x3, offset(x2); \
 302     li  x29, result; \
 303     bne x3, x29, fail; \
 304     addi  x4, x4, 1; \
 305     li  x5, 2; \
 306     bne x4, x5, 1b \
 307
 308 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 309 test_ ## testnum: \
 310     li  TESTNUM, testnum; \
 311     li  x4, 0; \
 312 1:  la  x2, base; \
 313     TEST_INSERT_NOPS_ ## src1_nops \
 314     la  x1, result; \
 315     TEST_INSERT_NOPS_ ## src2_nops \
 316     store_inst x1, offset(x2); \
 317     load_inst x3, offset(x2); \
 318     li  x29, result; \
 319     bne x3, x29, fail; \
 320     addi  x4, x4, 1; \
 321     li  x5, 2; \
 322     bne x4, x5, 1b \
 323
 324 #-----------------------------------------------------------------------
 325 # Test branch instructions
 326 #-----------------------------------------------------------------------
 327
 328 #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
 329 test_ ## testnum: \
 330     li  TESTNUM, testnum; \
 331     li  x1, val1; \
 332     inst x1, 2f; \
 333     bne x0, TESTNUM, fail; \
 334 1:  bne x0, TESTNUM, 3f; \
 335 2:  inst x1, 1b; \
 336     bne x0, TESTNUM, fail; \
 337 3:
 338
 339 #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
 340 test_ ## testnum: \
 341     li  TESTNUM, testnum; \
 342     li  x1, val1; \
 343     inst x1, 1f; \
 344     bne x0, TESTNUM, 2f; \
 345 1:  bne x0, TESTNUM, fail; \
 346 2:  inst x1, 1b; \
 347 3:
 348
 349 #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
 350 test_ ## testnum: \
 351     li  TESTNUM, testnum; \
 352     li  x4, 0; \
 353 1:  li  x1, val1; \
 354     TEST_INSERT_NOPS_ ## nop_cycles \
 355     inst x1, fail; \
 356     addi  x4, x4, 1; \
 357     li  x5, 2; \
 358     bne x4, x5, 1b \
 359
 360 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
 361 test_ ## testnum: \
 362     li  TESTNUM, testnum; \
 363     li  x1, val1; \
 364     li  x2, val2; \
 365     inst x1, x2, 2f; \
 366     bne x0, TESTNUM, fail; \
 367 1:  bne x0, TESTNUM, 3f; \
 368 2:  inst x1, x2, 1b; \
 369     bne x0, TESTNUM, fail; \
 370 3:
 371
 372 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 373 test_ ## testnum: \
 374     li  TESTNUM, testnum; \
 375     li  x1, val1; \
 376     li  x2, val2; \
 377     inst x1, x2, 1f; \
 378     bne x0, TESTNUM, 2f; \
 379 1:  bne x0, TESTNUM, fail; \
 380 2:  inst x1, x2, 1b; \
 381 3:
 382
 383 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 384 test_ ## testnum: \
 385     li  TESTNUM, testnum; \
 386     li  x4, 0; \
 387 1:  li  x1, val1; \
 388     TEST_INSERT_NOPS_ ## src1_nops \
 389     li  x2, val2; \
 390     TEST_INSERT_NOPS_ ## src2_nops \
 391     inst x1, x2, fail; \
 392     addi  x4, x4, 1; \
 393     li  x5, 2; \
 394     bne x4, x5, 1b \
 395
 396 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 397 test_ ## testnum: \
 398     li  TESTNUM, testnum; \
 399     li  x4, 0; \
 400 1:  li  x2, val2; \
 401     TEST_INSERT_NOPS_ ## src1_nops \
 402     li  x1, val1; \
 403     TEST_INSERT_NOPS_ ## src2_nops \
 404     inst x1, x2, fail; \
 405     addi  x4, x4, 1; \
 406     li  x5, 2; \
 407     bne x4, x5, 1b \
 408
 409 #-----------------------------------------------------------------------
 410 # Test jump instructions
 411 #-----------------------------------------------------------------------
 412
 413 #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 414 test_ ## testnum: \
 415     li  TESTNUM, testnum; \
 416     li  x4, 0; \
 417 1:  la  x6, 2f; \
 418     TEST_INSERT_NOPS_ ## nop_cycles \
 419     inst x6; \
 420     bne x0, TESTNUM, fail; \
 421 2:  addi  x4, x4, 1; \
 422     li  x5, 2; \
 423     bne x4, x5, 1b \
 424
 425 #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 426 test_ ## testnum: \
 427     li  TESTNUM, testnum; \
 428     li  x4, 0; \
 429 1:  la  x6, 2f; \
 430     TEST_INSERT_NOPS_ ## nop_cycles \
 431     inst x19, x6, 0; \
 432     bne x0, TESTNUM, fail; \
 433 2:  addi  x4, x4, 1; \
 434     li  x5, 2; \
 435     bne x4, x5, 1b \
 436
 437
 438 #-----------------------------------------------------------------------
 439 # RV64UF MACROS
 440 #-----------------------------------------------------------------------
 441
 442 #-----------------------------------------------------------------------
 443 # Tests floating-point instructions
 444 #-----------------------------------------------------------------------
 445
 446 #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
 447 test_ ## testnum: \
 448   li  TESTNUM, testnum; \
 449   la  a0, test_ ## testnum ## _data ;\
 450   flw f0, 0(a0); \
 451   flw f1, 4(a0); \
 452   flw f2, 8(a0); \
 453   lw  a3, 12(a0); \
 454   code; \
 455   fsflags a1, x0; \
 456   li a2, flags; \
 457   bne a0, a3, fail; \
 458   bne a1, a2, fail; \
 459   j 2f; \
 460   .align 2; \
 461   .data; \
 462   test_ ## testnum ## _data: \
 463   .float val1; \
 464   .float val2; \
 465   .float val3; \
 466   .result; \
 467   .text; \
 468 2:
 469
 470 #define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
 471 test_ ## testnum: \
 472   li  TESTNUM, testnum; \
 473   la  a0, test_ ## testnum ## _data ;\
 474   fld f0, 0(a0); \
 475   fld f1, 8(a0); \
 476   fld f2, 16(a0); \
 477   ld  a3, 24(a0); \
 478   code; \
 479   fsflags a1, x0; \
 480   li a2, flags; \
 481   bne a0, a3, fail; \
 482   bne a1, a2, fail; \
 483   j 2f; \
 484   .data; \
 485   .align 3; \
 486   test_ ## testnum ## _data: \
 487   .double val1; \
 488   .double val2; \
 489   .double val3; \
 490   .result; \
 491   .text; \
 492 2:
 493
 494 #define TEST_FCVT_S_D( testnum, result, val1 ) \
 495   TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
 496                     fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
 497
 498 #define TEST_FCVT_D_S( testnum, result, val1 ) \
 499   TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
 500                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
 501
 502 #define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
 503   TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
 504                     inst f3, f0; fmv.x.s a0, f3)
 505
 506 #define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
 507   TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
 508                     inst f3, f0; fmv.x.d a0, f3)
 509
 510 #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
 511   TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
 512                     inst f3, f0, f1; fmv.x.s a0, f3)
 513
 514 #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
 515   TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
 516                     inst f3, f0, f1; fmv.x.d a0, f3)
 517
 518 #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
 519   TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
 520                     inst f3, f0, f1, f2; fmv.x.s a0, f3)
 521
 522 #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
 523   TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
 524                     inst f3, f0, f1, f2; fmv.x.d a0, f3)
 525
 526 #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
 527   TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
 528                     inst a0, f0, rm)
 529
 530 #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
 531   TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
 532                     inst a0, f0, rm)
 533
 534 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
 535   TEST_FP_OP_S_INTERNAL( testnum, 0, word result, val1, val2, 0.0, \
 536                     inst a0, f0, f1)
 537
 538 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
 539   TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \
 540                     inst a0, f0, f1)
 541
 542 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 543 test_ ## testnum: \
 544   li  TESTNUM, testnum; \
 545   la  a0, test_ ## testnum ## _data ;\
 546   lw  a3, 0(a0); \
 547   li  a0, val1; \
 548   inst f0, a0; \
 549   fsflags x0; \
 550   fmv.x.s a0, f0; \
 551   bne a0, a3, fail; \
 552   b 1f; \
 553   .align 2; \
 554   test_ ## testnum ## _data: \
 555   .float result; \
 556 1:
 557
 558 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 559 test_ ## testnum: \
 560   li  TESTNUM, testnum; \
 561   la  a0, test_ ## testnum ## _data ;\
 562   ld  a3, 0(a0); \
 563   li  a0, val1; \
 564   inst f0, a0; \
 565   fsflags x0; \
 566   fmv.x.d a0, f0; \
 567   bne a0, a3, fail; \
 568   b 1f; \
 569   .align 3; \
 570   test_ ## testnum ## _data: \
 571   .double result; \
 572 1:
 573
 574
 575 #-----------------------------------------------------------------------
 576 # RV64SV MACROS
 577 #-----------------------------------------------------------------------
 578
 579 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
 580   csrs status, SR_EI; \
 581   la a0, handler ## testnum; \
 582   csrw evec, a0; \
 583   vsetcfg nxreg, nfreg; \
 584   li a0, 4; \
 585   vsetvl a0, a0; \
 586   la a0, src1; \
 587   la a1, src2; \
 588   vld vx2, a0; \
 589   vld vx3, a1; \
 590   lui a0,%hi(vtcode1 ## testnum); \
 591   vf %lo(vtcode1 ## testnum)(a0); \
 592   la reg2, dest; \
 593 illegal ## testnum: \
 594   inst reg1, reg2; \
 595   la a3, dest; \
 596   vsd vx2, a3; \
 597   fence; \
 598 vtcode1 ## testnum: \
 599   add x2, x2, x3; \
 600   stop; \
 601 vtcode2 ## testnum: \
 602   add x2, x2, x3; \
 603   stop; \
 604 handler ## testnum: \
 605   vxcptkill; \
 606   li TESTNUM,2; \
 607   vxcptcause a0; \
 608   li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
 609   bne a0,a1,fail; \
 610   vxcptaux a0; \
 611   la a1, illegal ## testnum; \
 612   lw a2, 0(a1); \
 613   bne a0, a2, fail; \
 614   vsetcfg 32,0; \
 615   li a0,4; \
 616   vsetvl a0,a0; \
 617   la a0,src1; \
 618   la a1,src2; \
 619   vld vx2,a0; \
 620   vld vx3,a1; \
 621   lui a0,%hi(vtcode2 ## testnum); \
 622   vf %lo(vtcode2 ## testnum)(a0); \
 623   la a3,dest; \
 624   vsd vx2,a3; \
 625   fence; \
 626   ld a1,0(a3); \
 627   li a2,5; \
 628   li TESTNUM,2; \
 629   bne a1,a2,fail; \
 630   ld a1,8(a3); \
 631   li TESTNUM,3; \
 632   bne a1,a2,fail; \
 633   ld a1,16(a3); \
 634   li TESTNUM,4; \
 635   bne a1,a2,fail; \
 636   ld a1,24(a3); \
 637   li TESTNUM,5; \
 638   bne a1,a2,fail; \
 639
 640 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
 641   csrs status, SR_EI; \
 642   la a0, handler ## testnum; \
 643   csrw evec, a0; \
 644   vsetcfg nxreg, nfreg; \
 645   li a0, 4; \
 646   vsetvl a0, a0; \
 647   la a0, src1; \
 648   la a1, src2; \
 649   vld vx2, a0; \
 650   vld vx3, a1; \
 651   lui a0,%hi(vtcode1 ## testnum); \
 652   vf %lo(vtcode1 ## testnum)(a0); \
 653   la a3, dest; \
 654   vsd vx2, a3; \
 655   fence; \
 656 vtcode1 ## testnum: \
 657   add x2, x2, x3; \
 658 illegal ## testnum: \
 659   inst reg1, reg2, reg3; \
 660   stop; \
 661 vtcode2 ## testnum: \
 662   add x2, x2, x3; \
 663   stop; \
 664 handler ## testnum: \
 665   vxcptkill; \
 666   li TESTNUM,2; \
 667   vxcptcause a0; \
 668   li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
 669   bne a0,a1,fail; \
 670   vxcptaux a0; \
 671   la a1,illegal ## testnum; \
 672   bne a0,a1,fail; \
 673   vsetcfg 32,0; \
 674   li a0,4; \
 675   vsetvl a0,a0; \
 676   la a0,src1; \
 677   la a1,src2; \
 678   vld vx2,a0; \
 679   vld vx3,a1; \
 680   lui a0,%hi(vtcode2 ## testnum); \
 681   vf %lo(vtcode2 ## testnum)(a0); \
 682   la a3,dest; \
 683   vsd vx2,a3; \
 684   fence; \
 685   ld a1,0(a3); \
 686   li a2,5; \
 687   li TESTNUM,2; \
 688   bne a1,a2,fail; \
 689   ld a1,8(a3); \
 690   li TESTNUM,3; \
 691   bne a1,a2,fail; \
 692   ld a1,16(a3); \
 693   li TESTNUM,4; \
 694   bne a1,a2,fail; \
 695   ld a1,24(a3); \
 696   li TESTNUM,5; \
 697   bne a1,a2,fail; \
 698
 699 #-----------------------------------------------------------------------
 700 # Pass and fail code (assumes test num is in TESTNUM)
 701 #-----------------------------------------------------------------------
 702
 703 #define TEST_PASSFAIL \
 704         bne x0, TESTNUM, pass; \
 705 fail: \
 706         RVTEST_FAIL \
 707 pass: \
 708         RVTEST_PASS \
 709
 710
 711 #-----------------------------------------------------------------------
 712 # Test data section
 713 #-----------------------------------------------------------------------
 714
 715 #define TEST_DATA
 716
 717 #endif