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[riscv-tests.git] / isa / macros / scalar / test_macros.h
1 #ifndef __TEST_MACROS_SCALAR_H
2 #define __TEST_MACROS_SCALAR_H
3
4
5 #-----------------------------------------------------------------------
6 # Helper macros
7 #-----------------------------------------------------------------------
8
9 #define TEST_CASE( testnum, testreg, correctval, code... ) \
10 test_ ## testnum: \
11 code; \
12 li x29, correctval; \
13 li TESTNUM, testnum; \
14 bne testreg, x29, fail;
15
16 # We use a macro hack to simpify code generation for various numbers
17 # of bubble cycles.
18
19 #define TEST_INSERT_NOPS_0
20 #define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
21 #define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
22 #define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
23 #define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
24 #define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
25 #define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
26 #define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
27 #define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
28 #define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
29 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
30
31
32 #-----------------------------------------------------------------------
33 # RV64UI MACROS
34 #-----------------------------------------------------------------------
35
36 #-----------------------------------------------------------------------
37 # Tests for instructions with immediate operand
38 #-----------------------------------------------------------------------
39
40 #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
41
42 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
43 TEST_CASE( testnum, x3, result, \
44 li x1, val1; \
45 inst x3, x1, SEXT_IMM(imm); \
46 )
47
48 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
49 TEST_CASE( testnum, x1, result, \
50 li x1, val1; \
51 inst x1, x1, SEXT_IMM(imm); \
52 )
53
54 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
55 TEST_CASE( testnum, x6, result, \
56 li x4, 0; \
57 1: li x1, val1; \
58 inst x3, x1, SEXT_IMM(imm); \
59 TEST_INSERT_NOPS_ ## nop_cycles \
60 addi x6, x3, 0; \
61 addi x4, x4, 1; \
62 li x5, 2; \
63 bne x4, x5, 1b \
64 )
65
66 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
67 TEST_CASE( testnum, x3, result, \
68 li x4, 0; \
69 1: li x1, val1; \
70 TEST_INSERT_NOPS_ ## nop_cycles \
71 inst x3, x1, SEXT_IMM(imm); \
72 addi x4, x4, 1; \
73 li x5, 2; \
74 bne x4, x5, 1b \
75 )
76
77 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
78 TEST_CASE( testnum, x1, result, \
79 inst x1, x0, SEXT_IMM(imm); \
80 )
81
82 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
83 TEST_CASE( testnum, x0, 0, \
84 li x1, val1; \
85 inst x0, x1, SEXT_IMM(imm); \
86 )
87
88 #-----------------------------------------------------------------------
89 # Tests for vector config instructions
90 #-----------------------------------------------------------------------
91
92 #define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
93 TEST_CASE( testnum, x1, result, \
94 li x1, (bank << 12); \
95 vsetcfg x1,nxpr,nfpr; \
96 li x1, vl; \
97 vsetvl x1,x1; \
98 )
99
100 #define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
101 TEST_CASE( testnum, x1, result, \
102 li x1, (bank << 12) | (nfpr << 6) | nxpr; \
103 vsetcfg x1; \
104 li x1, vl; \
105 vsetvl x1,x1; \
106 )
107
108 #define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
109 TEST_CASE( testnum, x1, result, \
110 li x1, (bank << 12); \
111 vsetcfg x1,nxpr,nfpr; \
112 li x1, vl; \
113 vsetvl x1, x1; \
114 )
115
116 #-----------------------------------------------------------------------
117 # Tests for an instruction with register operands
118 #-----------------------------------------------------------------------
119
120 #define TEST_R_OP( testnum, inst, result, val1 ) \
121 TEST_CASE( testnum, x3, result, \
122 li x1, val1; \
123 inst x3, x1; \
124 )
125
126 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
127 TEST_CASE( testnum, x1, result, \
128 li x1, val1; \
129 inst x1, x1; \
130 )
131
132 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
133 TEST_CASE( testnum, x6, result, \
134 li x4, 0; \
135 1: li x1, val1; \
136 inst x3, x1; \
137 TEST_INSERT_NOPS_ ## nop_cycles \
138 addi x6, x3, 0; \
139 addi x4, x4, 1; \
140 li x5, 2; \
141 bne x4, x5, 1b \
142 )
143
144 #-----------------------------------------------------------------------
145 # Tests for an instruction with register-register operands
146 #-----------------------------------------------------------------------
147
148 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
149 TEST_CASE( testnum, x3, result, \
150 li x1, val1; \
151 li x2, val2; \
152 inst x3, x1, x2; \
153 )
154
155 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
156 TEST_CASE( testnum, x1, result, \
157 li x1, val1; \
158 li x2, val2; \
159 inst x1, x1, x2; \
160 )
161
162 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
163 TEST_CASE( testnum, x2, result, \
164 li x1, val1; \
165 li x2, val2; \
166 inst x2, x1, x2; \
167 )
168
169 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
170 TEST_CASE( testnum, x1, result, \
171 li x1, val1; \
172 inst x1, x1, x1; \
173 )
174
175 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
176 TEST_CASE( testnum, x6, result, \
177 li x4, 0; \
178 1: li x1, val1; \
179 li x2, val2; \
180 inst x3, x1, x2; \
181 TEST_INSERT_NOPS_ ## nop_cycles \
182 addi x6, x3, 0; \
183 addi x4, x4, 1; \
184 li x5, 2; \
185 bne x4, x5, 1b \
186 )
187
188 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
189 TEST_CASE( testnum, x3, result, \
190 li x4, 0; \
191 1: li x1, val1; \
192 TEST_INSERT_NOPS_ ## src1_nops \
193 li x2, val2; \
194 TEST_INSERT_NOPS_ ## src2_nops \
195 inst x3, x1, x2; \
196 addi x4, x4, 1; \
197 li x5, 2; \
198 bne x4, x5, 1b \
199 )
200
201 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
202 TEST_CASE( testnum, x3, result, \
203 li x4, 0; \
204 1: li x2, val2; \
205 TEST_INSERT_NOPS_ ## src1_nops \
206 li x1, val1; \
207 TEST_INSERT_NOPS_ ## src2_nops \
208 inst x3, x1, x2; \
209 addi x4, x4, 1; \
210 li x5, 2; \
211 bne x4, x5, 1b \
212 )
213
214 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
215 TEST_CASE( testnum, x2, result, \
216 li x1, val; \
217 inst x2, x0, x1; \
218 )
219
220 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
221 TEST_CASE( testnum, x2, result, \
222 li x1, val; \
223 inst x2, x1, x0; \
224 )
225
226 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
227 TEST_CASE( testnum, x1, result, \
228 inst x1, x0, x0; \
229 )
230
231 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
232 TEST_CASE( testnum, x0, 0, \
233 li x1, val1; \
234 li x2, val2; \
235 inst x0, x1, x2; \
236 )
237
238 #-----------------------------------------------------------------------
239 # Test memory instructions
240 #-----------------------------------------------------------------------
241
242 #define TEST_LD_OP( testnum, inst, result, offset, base ) \
243 TEST_CASE( testnum, x3, result, \
244 la x1, base; \
245 inst x3, offset(x1); \
246 )
247
248 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
249 TEST_CASE( testnum, x3, result, \
250 la x1, base; \
251 li x2, result; \
252 store_inst x2, offset(x1); \
253 load_inst x3, offset(x1); \
254 )
255
256 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
257 test_ ## testnum: \
258 li TESTNUM, testnum; \
259 li x4, 0; \
260 1: la x1, base; \
261 inst x3, offset(x1); \
262 TEST_INSERT_NOPS_ ## nop_cycles \
263 addi x6, x3, 0; \
264 li x29, result; \
265 bne x6, x29, fail; \
266 addi x4, x4, 1; \
267 li x5, 2; \
268 bne x4, x5, 1b; \
269
270 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
271 test_ ## testnum: \
272 li TESTNUM, testnum; \
273 li x4, 0; \
274 1: la x1, base; \
275 TEST_INSERT_NOPS_ ## nop_cycles \
276 inst x3, offset(x1); \
277 li x29, result; \
278 bne x3, x29, fail; \
279 addi x4, x4, 1; \
280 li x5, 2; \
281 bne x4, x5, 1b \
282
283 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
284 test_ ## testnum: \
285 li TESTNUM, testnum; \
286 li x4, 0; \
287 1: la x1, result; \
288 TEST_INSERT_NOPS_ ## src1_nops \
289 la x2, base; \
290 TEST_INSERT_NOPS_ ## src2_nops \
291 store_inst x1, offset(x2); \
292 load_inst x3, offset(x2); \
293 li x29, result; \
294 bne x3, x29, fail; \
295 addi x4, x4, 1; \
296 li x5, 2; \
297 bne x4, x5, 1b \
298
299 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
300 test_ ## testnum: \
301 li TESTNUM, testnum; \
302 li x4, 0; \
303 1: la x2, base; \
304 TEST_INSERT_NOPS_ ## src1_nops \
305 la x1, result; \
306 TEST_INSERT_NOPS_ ## src2_nops \
307 store_inst x1, offset(x2); \
308 load_inst x3, offset(x2); \
309 li x29, result; \
310 bne x3, x29, fail; \
311 addi x4, x4, 1; \
312 li x5, 2; \
313 bne x4, x5, 1b \
314
315 #-----------------------------------------------------------------------
316 # Test branch instructions
317 #-----------------------------------------------------------------------
318
319 #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
320 test_ ## testnum: \
321 li TESTNUM, testnum; \
322 li x1, val1; \
323 inst x1, 2f; \
324 bne x0, TESTNUM, fail; \
325 1: bne x0, TESTNUM, 3f; \
326 2: inst x1, 1b; \
327 bne x0, TESTNUM, fail; \
328 3:
329
330 #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
331 test_ ## testnum: \
332 li TESTNUM, testnum; \
333 li x1, val1; \
334 inst x1, 1f; \
335 bne x0, TESTNUM, 2f; \
336 1: bne x0, TESTNUM, fail; \
337 2: inst x1, 1b; \
338 3:
339
340 #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
341 test_ ## testnum: \
342 li TESTNUM, testnum; \
343 li x4, 0; \
344 1: li x1, val1; \
345 TEST_INSERT_NOPS_ ## nop_cycles \
346 inst x1, fail; \
347 addi x4, x4, 1; \
348 li x5, 2; \
349 bne x4, x5, 1b \
350
351 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
352 test_ ## testnum: \
353 li TESTNUM, testnum; \
354 li x1, val1; \
355 li x2, val2; \
356 inst x1, x2, 2f; \
357 bne x0, TESTNUM, fail; \
358 1: bne x0, TESTNUM, 3f; \
359 2: inst x1, x2, 1b; \
360 bne x0, TESTNUM, fail; \
361 3:
362
363 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
364 test_ ## testnum: \
365 li TESTNUM, testnum; \
366 li x1, val1; \
367 li x2, val2; \
368 inst x1, x2, 1f; \
369 bne x0, TESTNUM, 2f; \
370 1: bne x0, TESTNUM, fail; \
371 2: inst x1, x2, 1b; \
372 3:
373
374 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
375 test_ ## testnum: \
376 li TESTNUM, testnum; \
377 li x4, 0; \
378 1: li x1, val1; \
379 TEST_INSERT_NOPS_ ## src1_nops \
380 li x2, val2; \
381 TEST_INSERT_NOPS_ ## src2_nops \
382 inst x1, x2, fail; \
383 addi x4, x4, 1; \
384 li x5, 2; \
385 bne x4, x5, 1b \
386
387 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
388 test_ ## testnum: \
389 li TESTNUM, testnum; \
390 li x4, 0; \
391 1: li x2, val2; \
392 TEST_INSERT_NOPS_ ## src1_nops \
393 li x1, val1; \
394 TEST_INSERT_NOPS_ ## src2_nops \
395 inst x1, x2, fail; \
396 addi x4, x4, 1; \
397 li x5, 2; \
398 bne x4, x5, 1b \
399
400 #-----------------------------------------------------------------------
401 # Test jump instructions
402 #-----------------------------------------------------------------------
403
404 #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
405 test_ ## testnum: \
406 li TESTNUM, testnum; \
407 li x4, 0; \
408 1: la x6, 2f; \
409 TEST_INSERT_NOPS_ ## nop_cycles \
410 inst x6; \
411 bne x0, TESTNUM, fail; \
412 2: addi x4, x4, 1; \
413 li x5, 2; \
414 bne x4, x5, 1b \
415
416 #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
417 test_ ## testnum: \
418 li TESTNUM, testnum; \
419 li x4, 0; \
420 1: la x6, 2f; \
421 TEST_INSERT_NOPS_ ## nop_cycles \
422 inst x19, x6, 0; \
423 bne x0, TESTNUM, fail; \
424 2: addi x4, x4, 1; \
425 li x5, 2; \
426 bne x4, x5, 1b \
427
428
429 #-----------------------------------------------------------------------
430 # RV64UF MACROS
431 #-----------------------------------------------------------------------
432
433 #-----------------------------------------------------------------------
434 # Tests floating-point instructions
435 #-----------------------------------------------------------------------
436
437 #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
438 test_ ## testnum: \
439 li TESTNUM, testnum; \
440 la a0, test_ ## testnum ## _data ;\
441 flw f0, 0(a0); \
442 flw f1, 4(a0); \
443 flw f2, 8(a0); \
444 lw a3, 12(a0); \
445 code; \
446 fsflags a1, x0; \
447 li a2, flags; \
448 bne a0, a3, fail; \
449 bne a1, a2, fail; \
450 j 2f; \
451 .align 2; \
452 .data; \
453 test_ ## testnum ## _data: \
454 .float val1; \
455 .float val2; \
456 .float val3; \
457 .result; \
458 .text; \
459 2:
460
461 #define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
462 test_ ## testnum: \
463 li TESTNUM, testnum; \
464 la a0, test_ ## testnum ## _data ;\
465 fld f0, 0(a0); \
466 fld f1, 8(a0); \
467 fld f2, 16(a0); \
468 ld a3, 24(a0); \
469 code; \
470 fsflags a1, x0; \
471 li a2, flags; \
472 bne a0, a3, fail; \
473 bne a1, a2, fail; \
474 j 2f; \
475 .data; \
476 .align 3; \
477 test_ ## testnum ## _data: \
478 .double val1; \
479 .double val2; \
480 .double val3; \
481 .result; \
482 .text; \
483 2:
484
485 #define TEST_FCVT_S_D( testnum, result, val1 ) \
486 TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
487 fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
488
489 #define TEST_FCVT_D_S( testnum, result, val1 ) \
490 TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
491 fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
492
493 #define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
494 TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
495 inst f3, f0; fmv.x.s a0, f3)
496
497 #define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
498 TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
499 inst f3, f0; fmv.x.d a0, f3)
500
501 #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
502 TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
503 inst f3, f0, f1; fmv.x.s a0, f3)
504
505 #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
506 TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
507 inst f3, f0, f1; fmv.x.d a0, f3)
508
509 #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
510 TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
511 inst f3, f0, f1, f2; fmv.x.s a0, f3)
512
513 #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
514 TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
515 inst f3, f0, f1, f2; fmv.x.d a0, f3)
516
517 #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
518 TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
519 inst a0, f0, rm)
520
521 #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
522 TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
523 inst a0, f0, rm)
524
525 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
526 TEST_FP_OP_S_INTERNAL( testnum, 0, word result, val1, val2, 0.0, \
527 inst a0, f0, f1)
528
529 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
530 TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \
531 inst a0, f0, f1)
532
533 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
534 test_ ## testnum: \
535 li TESTNUM, testnum; \
536 la a0, test_ ## testnum ## _data ;\
537 lw a3, 0(a0); \
538 li a0, val1; \
539 inst f0, a0; \
540 fsflags x0; \
541 fmv.x.s a0, f0; \
542 bne a0, a3, fail; \
543 b 1f; \
544 .align 2; \
545 test_ ## testnum ## _data: \
546 .float result; \
547 1:
548
549 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
550 test_ ## testnum: \
551 li TESTNUM, testnum; \
552 la a0, test_ ## testnum ## _data ;\
553 ld a3, 0(a0); \
554 li a0, val1; \
555 inst f0, a0; \
556 fsflags x0; \
557 fmv.x.d a0, f0; \
558 bne a0, a3, fail; \
559 b 1f; \
560 .align 3; \
561 test_ ## testnum ## _data: \
562 .double result; \
563 1:
564
565
566 #-----------------------------------------------------------------------
567 # RV64SV MACROS
568 #-----------------------------------------------------------------------
569
570 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
571 csrs status, SR_EI; \
572 la a0, handler ## testnum; \
573 csrw evec, a0; \
574 vsetcfg nxreg, nfreg; \
575 li a0, 4; \
576 vsetvl a0, a0; \
577 la a0, src1; \
578 la a1, src2; \
579 vld vx2, a0; \
580 vld vx3, a1; \
581 lui a0,%hi(vtcode1 ## testnum); \
582 vf %lo(vtcode1 ## testnum)(a0); \
583 la reg2, dest; \
584 illegal ## testnum: \
585 inst reg1, reg2; \
586 la a3, dest; \
587 vsd vx2, a3; \
588 fence; \
589 vtcode1 ## testnum: \
590 add x2, x2, x3; \
591 stop; \
592 vtcode2 ## testnum: \
593 add x2, x2, x3; \
594 stop; \
595 handler ## testnum: \
596 vxcptkill; \
597 li TESTNUM,2; \
598 vxcptcause a0; \
599 li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
600 bne a0,a1,fail; \
601 vxcptaux a0; \
602 la a1, illegal ## testnum; \
603 lw a2, 0(a1); \
604 bne a0, a2, fail; \
605 vsetcfg 32,0; \
606 li a0,4; \
607 vsetvl a0,a0; \
608 la a0,src1; \
609 la a1,src2; \
610 vld vx2,a0; \
611 vld vx3,a1; \
612 lui a0,%hi(vtcode2 ## testnum); \
613 vf %lo(vtcode2 ## testnum)(a0); \
614 la a3,dest; \
615 vsd vx2,a3; \
616 fence; \
617 ld a1,0(a3); \
618 li a2,5; \
619 li TESTNUM,2; \
620 bne a1,a2,fail; \
621 ld a1,8(a3); \
622 li TESTNUM,3; \
623 bne a1,a2,fail; \
624 ld a1,16(a3); \
625 li TESTNUM,4; \
626 bne a1,a2,fail; \
627 ld a1,24(a3); \
628 li TESTNUM,5; \
629 bne a1,a2,fail; \
630
631 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
632 csrs status, SR_EI; \
633 la a0, handler ## testnum; \
634 csrw evec, a0; \
635 vsetcfg nxreg, nfreg; \
636 li a0, 4; \
637 vsetvl a0, a0; \
638 la a0, src1; \
639 la a1, src2; \
640 vld vx2, a0; \
641 vld vx3, a1; \
642 lui a0,%hi(vtcode1 ## testnum); \
643 vf %lo(vtcode1 ## testnum)(a0); \
644 la a3, dest; \
645 vsd vx2, a3; \
646 fence; \
647 vtcode1 ## testnum: \
648 add x2, x2, x3; \
649 illegal ## testnum: \
650 inst reg1, reg2, reg3; \
651 stop; \
652 vtcode2 ## testnum: \
653 add x2, x2, x3; \
654 stop; \
655 handler ## testnum: \
656 vxcptkill; \
657 li TESTNUM,2; \
658 vxcptcause a0; \
659 li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
660 bne a0,a1,fail; \
661 vxcptaux a0; \
662 la a1,illegal ## testnum; \
663 bne a0,a1,fail; \
664 vsetcfg 32,0; \
665 li a0,4; \
666 vsetvl a0,a0; \
667 la a0,src1; \
668 la a1,src2; \
669 vld vx2,a0; \
670 vld vx3,a1; \
671 lui a0,%hi(vtcode2 ## testnum); \
672 vf %lo(vtcode2 ## testnum)(a0); \
673 la a3,dest; \
674 vsd vx2,a3; \
675 fence; \
676 ld a1,0(a3); \
677 li a2,5; \
678 li TESTNUM,2; \
679 bne a1,a2,fail; \
680 ld a1,8(a3); \
681 li TESTNUM,3; \
682 bne a1,a2,fail; \
683 ld a1,16(a3); \
684 li TESTNUM,4; \
685 bne a1,a2,fail; \
686 ld a1,24(a3); \
687 li TESTNUM,5; \
688 bne a1,a2,fail; \
689
690 #-----------------------------------------------------------------------
691 # Pass and fail code (assumes test num is in TESTNUM)
692 #-----------------------------------------------------------------------
693
694 #define TEST_PASSFAIL \
695 bne x0, TESTNUM, pass; \
696 fail: \
697 RVTEST_FAIL \
698 pass: \
699 RVTEST_PASS \
700
701
702 #-----------------------------------------------------------------------
703 # Test data section
704 #-----------------------------------------------------------------------
705
706 #define TEST_DATA
707
708 #endif