isa/macros/scalar/test_macros.h

   1 // See LICENSE for license details.
   2
   3 #ifndef __TEST_MACROS_SCALAR_H
   4 #define __TEST_MACROS_SCALAR_H
   5
   6
   7 #-----------------------------------------------------------------------
   8 # Helper macros
   9 #-----------------------------------------------------------------------
  10
  11 #define TEST_CASE( testnum, testreg, correctval, code... ) \
  12 test_ ## testnum: \
  13     code; \
  14     li  x29, correctval; \
  15     li  TESTNUM, testnum; \
  16     bne testreg, x29, fail;
  17
  18 # We use a macro hack to simpify code generation for various numbers
  19 # of bubble cycles.
  20
  21 #define TEST_INSERT_NOPS_0
  22 #define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
  23 #define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
  24 #define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
  25 #define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
  26 #define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
  27 #define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
  28 #define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
  29 #define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
  30 #define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
  31 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
  32
  33
  34 #-----------------------------------------------------------------------
  35 # RV64UI MACROS
  36 #-----------------------------------------------------------------------
  37
  38 #-----------------------------------------------------------------------
  39 # Tests for instructions with immediate operand
  40 #-----------------------------------------------------------------------
  41
  42 #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
  43
  44 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
  45     TEST_CASE( testnum, x3, result, \
  46       li  x1, val1; \
  47       inst x3, x1, SEXT_IMM(imm); \
  48     )
  49
  50 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
  51     TEST_CASE( testnum, x1, result, \
  52       li  x1, val1; \
  53       inst x1, x1, SEXT_IMM(imm); \
  54     )
  55
  56 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  57     TEST_CASE( testnum, x6, result, \
  58       li  x4, 0; \
  59 1:    li  x1, val1; \
  60       inst x3, x1, SEXT_IMM(imm); \
  61       TEST_INSERT_NOPS_ ## nop_cycles \
  62       addi  x6, x3, 0; \
  63       addi  x4, x4, 1; \
  64       li  x5, 2; \
  65       bne x4, x5, 1b \
  66     )
  67
  68 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  69     TEST_CASE( testnum, x3, result, \
  70       li  x4, 0; \
  71 1:    li  x1, val1; \
  72       TEST_INSERT_NOPS_ ## nop_cycles \
  73       inst x3, x1, SEXT_IMM(imm); \
  74       addi  x4, x4, 1; \
  75       li  x5, 2; \
  76       bne x4, x5, 1b \
  77     )
  78
  79 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
  80     TEST_CASE( testnum, x1, result, \
  81       inst x1, x0, SEXT_IMM(imm); \
  82     )
  83
  84 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
  85     TEST_CASE( testnum, x0, 0, \
  86       li  x1, val1; \
  87       inst x0, x1, SEXT_IMM(imm); \
  88     )
  89
  90 #-----------------------------------------------------------------------
  91 # Tests for vector config instructions
  92 #-----------------------------------------------------------------------
  93
  94 #define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
  95     TEST_CASE( testnum, x1, result, \
  96       li x1, (bank << 12); \
  97       vsetcfg x1,nxpr,nfpr; \
  98       li x1, vl; \
  99       vsetvl x1,x1; \
 100     )
 101
 102 #define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
 103     TEST_CASE( testnum, x1, result, \
 104       li x1, (bank << 12) | (nfpr << 6) | nxpr; \
 105       vsetcfg x1; \
 106       li x1, vl; \
 107       vsetvl x1,x1; \
 108     )
 109
 110 #define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
 111     TEST_CASE( testnum, x1, result, \
 112       li x1, (bank << 12); \
 113       vsetcfg x1,nxpr,nfpr; \
 114       li x1, vl; \
 115       vsetvl x1, x1; \
 116     )
 117
 118 #-----------------------------------------------------------------------
 119 # Tests for an instruction with register operands
 120 #-----------------------------------------------------------------------
 121
 122 #define TEST_R_OP( testnum, inst, result, val1 ) \
 123     TEST_CASE( testnum, x3, result, \
 124       li  x1, val1; \
 125       inst x3, x1; \
 126     )
 127
 128 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
 129     TEST_CASE( testnum, x1, result, \
 130       li  x1, val1; \
 131       inst x1, x1; \
 132     )
 133
 134 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
 135     TEST_CASE( testnum, x6, result, \
 136       li  x4, 0; \
 137 1:    li  x1, val1; \
 138       inst x3, x1; \
 139       TEST_INSERT_NOPS_ ## nop_cycles \
 140       addi  x6, x3, 0; \
 141       addi  x4, x4, 1; \
 142       li  x5, 2; \
 143       bne x4, x5, 1b \
 144     )
 145
 146 #-----------------------------------------------------------------------
 147 # Tests for an instruction with register-register operands
 148 #-----------------------------------------------------------------------
 149
 150 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
 151     TEST_CASE( testnum, x3, result, \
 152       li  x1, val1; \
 153       li  x2, val2; \
 154       inst x3, x1, x2; \
 155     )
 156
 157 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
 158     TEST_CASE( testnum, x1, result, \
 159       li  x1, val1; \
 160       li  x2, val2; \
 161       inst x1, x1, x2; \
 162     )
 163
 164 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
 165     TEST_CASE( testnum, x2, result, \
 166       li  x1, val1; \
 167       li  x2, val2; \
 168       inst x2, x1, x2; \
 169     )
 170
 171 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
 172     TEST_CASE( testnum, x1, result, \
 173       li  x1, val1; \
 174       inst x1, x1, x1; \
 175     )
 176
 177 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
 178     TEST_CASE( testnum, x6, result, \
 179       li  x4, 0; \
 180 1:    li  x1, val1; \
 181       li  x2, val2; \
 182       inst x3, x1, x2; \
 183       TEST_INSERT_NOPS_ ## nop_cycles \
 184       addi  x6, x3, 0; \
 185       addi  x4, x4, 1; \
 186       li  x5, 2; \
 187       bne x4, x5, 1b \
 188     )
 189
 190 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 191     TEST_CASE( testnum, x3, result, \
 192       li  x4, 0; \
 193 1:    li  x1, val1; \
 194       TEST_INSERT_NOPS_ ## src1_nops \
 195       li  x2, val2; \
 196       TEST_INSERT_NOPS_ ## src2_nops \
 197       inst x3, x1, x2; \
 198       addi  x4, x4, 1; \
 199       li  x5, 2; \
 200       bne x4, x5, 1b \
 201     )
 202
 203 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 204     TEST_CASE( testnum, x3, result, \
 205       li  x4, 0; \
 206 1:    li  x2, val2; \
 207       TEST_INSERT_NOPS_ ## src1_nops \
 208       li  x1, val1; \
 209       TEST_INSERT_NOPS_ ## src2_nops \
 210       inst x3, x1, x2; \
 211       addi  x4, x4, 1; \
 212       li  x5, 2; \
 213       bne x4, x5, 1b \
 214     )
 215
 216 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
 217     TEST_CASE( testnum, x2, result, \
 218       li x1, val; \
 219       inst x2, x0, x1; \
 220     )
 221
 222 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
 223     TEST_CASE( testnum, x2, result, \
 224       li x1, val; \
 225       inst x2, x1, x0; \
 226     )
 227
 228 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
 229     TEST_CASE( testnum, x1, result, \
 230       inst x1, x0, x0; \
 231     )
 232
 233 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
 234     TEST_CASE( testnum, x0, 0, \
 235       li x1, val1; \
 236       li x2, val2; \
 237       inst x0, x1, x2; \
 238     )
 239
 240 #-----------------------------------------------------------------------
 241 # Test memory instructions
 242 #-----------------------------------------------------------------------
 243
 244 #define TEST_LD_OP( testnum, inst, result, offset, base ) \
 245     TEST_CASE( testnum, x3, result, \
 246       la  x1, base; \
 247       inst x3, offset(x1); \
 248     )
 249
 250 #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
 251     TEST_CASE( testnum, x3, result, \
 252       la  x1, base; \
 253       li  x2, result; \
 254       store_inst x2, offset(x1); \
 255       load_inst x3, offset(x1); \
 256     )
 257
 258 #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 259 test_ ## testnum: \
 260     li  TESTNUM, testnum; \
 261     li  x4, 0; \
 262 1:  la  x1, base; \
 263     inst x3, offset(x1); \
 264     TEST_INSERT_NOPS_ ## nop_cycles \
 265     addi  x6, x3, 0; \
 266     li  x29, result; \
 267     bne x6, x29, fail; \
 268     addi  x4, x4, 1; \
 269     li  x5, 2; \
 270     bne x4, x5, 1b; \
 271
 272 #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
 273 test_ ## testnum: \
 274     li  TESTNUM, testnum; \
 275     li  x4, 0; \
 276 1:  la  x1, base; \
 277     TEST_INSERT_NOPS_ ## nop_cycles \
 278     inst x3, offset(x1); \
 279     li  x29, result; \
 280     bne x3, x29, fail; \
 281     addi  x4, x4, 1; \
 282     li  x5, 2; \
 283     bne x4, x5, 1b \
 284
 285 #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 286 test_ ## testnum: \
 287     li  TESTNUM, testnum; \
 288     li  x4, 0; \
 289 1:  la  x1, result; \
 290     TEST_INSERT_NOPS_ ## src1_nops \
 291     la  x2, base; \
 292     TEST_INSERT_NOPS_ ## src2_nops \
 293     store_inst x1, offset(x2); \
 294     load_inst x3, offset(x2); \
 295     li  x29, result; \
 296     bne x3, x29, fail; \
 297     addi  x4, x4, 1; \
 298     li  x5, 2; \
 299     bne x4, x5, 1b \
 300
 301 #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
 302 test_ ## testnum: \
 303     li  TESTNUM, testnum; \
 304     li  x4, 0; \
 305 1:  la  x2, base; \
 306     TEST_INSERT_NOPS_ ## src1_nops \
 307     la  x1, result; \
 308     TEST_INSERT_NOPS_ ## src2_nops \
 309     store_inst x1, offset(x2); \
 310     load_inst x3, offset(x2); \
 311     li  x29, result; \
 312     bne x3, x29, fail; \
 313     addi  x4, x4, 1; \
 314     li  x5, 2; \
 315     bne x4, x5, 1b \
 316
 317 #-----------------------------------------------------------------------
 318 # Test branch instructions
 319 #-----------------------------------------------------------------------
 320
 321 #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
 322 test_ ## testnum: \
 323     li  TESTNUM, testnum; \
 324     li  x1, val1; \
 325     inst x1, 2f; \
 326     bne x0, TESTNUM, fail; \
 327 1:  bne x0, TESTNUM, 3f; \
 328 2:  inst x1, 1b; \
 329     bne x0, TESTNUM, fail; \
 330 3:
 331
 332 #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
 333 test_ ## testnum: \
 334     li  TESTNUM, testnum; \
 335     li  x1, val1; \
 336     inst x1, 1f; \
 337     bne x0, TESTNUM, 2f; \
 338 1:  bne x0, TESTNUM, fail; \
 339 2:  inst x1, 1b; \
 340 3:
 341
 342 #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
 343 test_ ## testnum: \
 344     li  TESTNUM, testnum; \
 345     li  x4, 0; \
 346 1:  li  x1, val1; \
 347     TEST_INSERT_NOPS_ ## nop_cycles \
 348     inst x1, fail; \
 349     addi  x4, x4, 1; \
 350     li  x5, 2; \
 351     bne x4, x5, 1b \
 352
 353 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
 354 test_ ## testnum: \
 355     li  TESTNUM, testnum; \
 356     li  x1, val1; \
 357     li  x2, val2; \
 358     inst x1, x2, 2f; \
 359     bne x0, TESTNUM, fail; \
 360 1:  bne x0, TESTNUM, 3f; \
 361 2:  inst x1, x2, 1b; \
 362     bne x0, TESTNUM, fail; \
 363 3:
 364
 365 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 366 test_ ## testnum: \
 367     li  TESTNUM, testnum; \
 368     li  x1, val1; \
 369     li  x2, val2; \
 370     inst x1, x2, 1f; \
 371     bne x0, TESTNUM, 2f; \
 372 1:  bne x0, TESTNUM, fail; \
 373 2:  inst x1, x2, 1b; \
 374 3:
 375
 376 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 377 test_ ## testnum: \
 378     li  TESTNUM, testnum; \
 379     li  x4, 0; \
 380 1:  li  x1, val1; \
 381     TEST_INSERT_NOPS_ ## src1_nops \
 382     li  x2, val2; \
 383     TEST_INSERT_NOPS_ ## src2_nops \
 384     inst x1, x2, fail; \
 385     addi  x4, x4, 1; \
 386     li  x5, 2; \
 387     bne x4, x5, 1b \
 388
 389 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 390 test_ ## testnum: \
 391     li  TESTNUM, testnum; \
 392     li  x4, 0; \
 393 1:  li  x2, val2; \
 394     TEST_INSERT_NOPS_ ## src1_nops \
 395     li  x1, val1; \
 396     TEST_INSERT_NOPS_ ## src2_nops \
 397     inst x1, x2, fail; \
 398     addi  x4, x4, 1; \
 399     li  x5, 2; \
 400     bne x4, x5, 1b \
 401
 402 #-----------------------------------------------------------------------
 403 # Test jump instructions
 404 #-----------------------------------------------------------------------
 405
 406 #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 407 test_ ## testnum: \
 408     li  TESTNUM, testnum; \
 409     li  x4, 0; \
 410 1:  la  x6, 2f; \
 411     TEST_INSERT_NOPS_ ## nop_cycles \
 412     inst x6; \
 413     bne x0, TESTNUM, fail; \
 414 2:  addi  x4, x4, 1; \
 415     li  x5, 2; \
 416     bne x4, x5, 1b \
 417
 418 #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
 419 test_ ## testnum: \
 420     li  TESTNUM, testnum; \
 421     li  x4, 0; \
 422 1:  la  x6, 2f; \
 423     TEST_INSERT_NOPS_ ## nop_cycles \
 424     inst x19, x6, 0; \
 425     bne x0, TESTNUM, fail; \
 426 2:  addi  x4, x4, 1; \
 427     li  x5, 2; \
 428     bne x4, x5, 1b \
 429
 430
 431 #-----------------------------------------------------------------------
 432 # RV64UF MACROS
 433 #-----------------------------------------------------------------------
 434
 435 #-----------------------------------------------------------------------
 436 # Tests floating-point instructions
 437 #-----------------------------------------------------------------------
 438
 439 #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
 440 test_ ## testnum: \
 441   li  TESTNUM, testnum; \
 442   la  a0, test_ ## testnum ## _data ;\
 443   flw f0, 0(a0); \
 444   flw f1, 4(a0); \
 445   flw f2, 8(a0); \
 446   lw  a3, 12(a0); \
 447   code; \
 448   fsflags a1, x0; \
 449   li a2, flags; \
 450   bne a0, a3, fail; \
 451   bne a1, a2, fail; \
 452   j 2f; \
 453   .align 2; \
 454   .data; \
 455   test_ ## testnum ## _data: \
 456   .float val1; \
 457   .float val2; \
 458   .float val3; \
 459   .result; \
 460   .text; \
 461 2:
 462
 463 #define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
 464 test_ ## testnum: \
 465   li  TESTNUM, testnum; \
 466   la  a0, test_ ## testnum ## _data ;\
 467   fld f0, 0(a0); \
 468   fld f1, 8(a0); \
 469   fld f2, 16(a0); \
 470   ld  a3, 24(a0); \
 471   code; \
 472   fsflags a1, x0; \
 473   li a2, flags; \
 474   bne a0, a3, fail; \
 475   bne a1, a2, fail; \
 476   j 2f; \
 477   .data; \
 478   .align 3; \
 479   test_ ## testnum ## _data: \
 480   .double val1; \
 481   .double val2; \
 482   .double val3; \
 483   .result; \
 484   .text; \
 485 2:
 486
 487 #define TEST_FCVT_S_D( testnum, result, val1 ) \
 488   TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
 489                     fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
 490
 491 #define TEST_FCVT_D_S( testnum, result, val1 ) \
 492   TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
 493                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
 494
 495 #define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
 496   TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
 497                     inst f3, f0; fmv.x.s a0, f3)
 498
 499 #define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
 500   TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
 501                     inst f3, f0; fmv.x.d a0, f3)
 502
 503 #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
 504   TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
 505                     inst f3, f0, f1; fmv.x.s a0, f3)
 506
 507 #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
 508   TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
 509                     inst f3, f0, f1; fmv.x.d a0, f3)
 510
 511 #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
 512   TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
 513                     inst f3, f0, f1, f2; fmv.x.s a0, f3)
 514
 515 #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
 516   TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
 517                     inst f3, f0, f1, f2; fmv.x.d a0, f3)
 518
 519 #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
 520   TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
 521                     inst a0, f0, rm)
 522
 523 #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
 524   TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
 525                     inst a0, f0, rm)
 526
 527 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
 528   TEST_FP_OP_S_INTERNAL( testnum, 0, word result, val1, val2, 0.0, \
 529                     inst a0, f0, f1)
 530
 531 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
 532   TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \
 533                     inst a0, f0, f1)
 534
 535 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 536 test_ ## testnum: \
 537   li  TESTNUM, testnum; \
 538   la  a0, test_ ## testnum ## _data ;\
 539   lw  a3, 0(a0); \
 540   li  a0, val1; \
 541   inst f0, a0; \
 542   fsflags x0; \
 543   fmv.x.s a0, f0; \
 544   bne a0, a3, fail; \
 545   j 1f; \
 546   .align 2; \
 547   test_ ## testnum ## _data: \
 548   .float result; \
 549 1:
 550
 551 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 552 test_ ## testnum: \
 553   li  TESTNUM, testnum; \
 554   la  a0, test_ ## testnum ## _data ;\
 555   ld  a3, 0(a0); \
 556   li  a0, val1; \
 557   inst f0, a0; \
 558   fsflags x0; \
 559   fmv.x.d a0, f0; \
 560   bne a0, a3, fail; \
 561   j 1f; \
 562   .align 3; \
 563   test_ ## testnum ## _data: \
 564   .double result; \
 565 1:
 566
 567
 568 #-----------------------------------------------------------------------
 569 # RV64SV MACROS
 570 #-----------------------------------------------------------------------
 571
 572 #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
 573   la a0, handler ## testnum; \
 574   csrw stvec, a0; \
 575   vsetcfg nxreg, nfreg; \
 576   li a0, 4; \
 577   vsetvl a0, a0; \
 578   la a0, src1; \
 579   la a1, src2; \
 580   vld vx2, a0; \
 581   vld vx3, a1; \
 582   lui a0,%hi(vtcode1 ## testnum); \
 583   vf %lo(vtcode1 ## testnum)(a0); \
 584   la reg2, dest; \
 585 illegal ## testnum: \
 586   inst reg1, reg2; \
 587   la a3, dest; \
 588   vsd vx2, a3; \
 589   fence; \
 590 vtcode1 ## testnum: \
 591   add x2, x2, x3; \
 592   stop; \
 593 vtcode2 ## testnum: \
 594   add x2, x2, x3; \
 595   stop; \
 596 handler ## testnum: \
 597   vxcptkill; \
 598   li TESTNUM,2; \
 599   csrr a0, scause; \
 600   li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
 601   bne a0,a1,fail; \
 602   csrr a0, sbadaddr; \
 603   la a1, illegal ## testnum; \
 604   lw a2, 0(a1); \
 605   bne a0, a2, fail; \
 606   vsetcfg 32,0; \
 607   li a0,4; \
 608   vsetvl a0,a0; \
 609   la a0,src1; \
 610   la a1,src2; \
 611   vld vx2,a0; \
 612   vld vx3,a1; \
 613   lui a0,%hi(vtcode2 ## testnum); \
 614   vf %lo(vtcode2 ## testnum)(a0); \
 615   la a3,dest; \
 616   vsd vx2,a3; \
 617   fence; \
 618   ld a1,0(a3); \
 619   li a2,5; \
 620   li TESTNUM,2; \
 621   bne a1,a2,fail; \
 622   ld a1,8(a3); \
 623   li TESTNUM,3; \
 624   bne a1,a2,fail; \
 625   ld a1,16(a3); \
 626   li TESTNUM,4; \
 627   bne a1,a2,fail; \
 628   ld a1,24(a3); \
 629   li TESTNUM,5; \
 630   bne a1,a2,fail; \
 631
 632 #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
 633   la a0, handler ## testnum; \
 634   csrw stvec, a0; \
 635   vsetcfg nxreg, nfreg; \
 636   li a0, 4; \
 637   vsetvl a0, a0; \
 638   la a0, src1; \
 639   la a1, src2; \
 640   vld vx2, a0; \
 641   vld vx3, a1; \
 642   lui a0,%hi(vtcode1 ## testnum); \
 643   vf %lo(vtcode1 ## testnum)(a0); \
 644   la a3, dest; \
 645   vsd vx2, a3; \
 646   fence; \
 647 vtcode1 ## testnum: \
 648   add x2, x2, x3; \
 649 illegal ## testnum: \
 650   inst reg1, reg2, reg3; \
 651   stop; \
 652 vtcode2 ## testnum: \
 653   add x2, x2, x3; \
 654   stop; \
 655 handler ## testnum: \
 656   vxcptkill; \
 657   li TESTNUM,2; \
 658   csrr a0, scause; \
 659   li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
 660   bne a0,a1,fail; \
 661   csrr a0, sbadaddr; \
 662   la a1,illegal ## testnum; \
 663   bne a0,a1,fail; \
 664   vsetcfg 32,0; \
 665   li a0,4; \
 666   vsetvl a0,a0; \
 667   la a0,src1; \
 668   la a1,src2; \
 669   vld vx2,a0; \
 670   vld vx3,a1; \
 671   lui a0,%hi(vtcode2 ## testnum); \
 672   vf %lo(vtcode2 ## testnum)(a0); \
 673   la a3,dest; \
 674   vsd vx2,a3; \
 675   fence; \
 676   ld a1,0(a3); \
 677   li a2,5; \
 678   li TESTNUM,2; \
 679   bne a1,a2,fail; \
 680   ld a1,8(a3); \
 681   li TESTNUM,3; \
 682   bne a1,a2,fail; \
 683   ld a1,16(a3); \
 684   li TESTNUM,4; \
 685   bne a1,a2,fail; \
 686   ld a1,24(a3); \
 687   li TESTNUM,5; \
 688   bne a1,a2,fail; \
 689
 690 #-----------------------------------------------------------------------
 691 # Pass and fail code (assumes test num is in TESTNUM)
 692 #-----------------------------------------------------------------------
 693
 694 #define TEST_PASSFAIL \
 695         bne x0, TESTNUM, pass; \
 696 fail: \
 697         RVTEST_FAIL; \
 698 pass: \
 699         RVTEST_PASS \
 700
 701
 702 #-----------------------------------------------------------------------
 703 # Test data section
 704 #-----------------------------------------------------------------------
 705
 706 #define TEST_DATA
 707
 708 #endif