isa/macros/simplev/sv_test_macros.h

   1 #define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
   2
   3 #define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
   4   (reg0 | (reg1<<8) | (reg2<<8) | \
   5    (shape0<<24) | (shape0<<26) | (shape0<<28))
   6
   7 #define SV_SHAPE_PERM_XYZ 0
   8 #define SV_SHAPE_PERM_XZY 1
   9 #define SV_SHAPE_PERM_YXZ 2
  10 #define SV_SHAPE_PERM_YZX 3
  11 #define SV_SHAPE_PERM_ZXY 4
  12 #define SV_SHAPE_PERM_ZYX 5
  13
  14 #define SV_SHAPE_CSR(xd, yd, zd, offs, perm) \
  15   ((xd-1) | ((yd-1)<<8) | ((zd-1)<<16) | (perm<<24) | \
  16    ((offs&0x1)<<7) | ((offs&0x2)<<14) | ((offs&0x4)<<21) )
  17
  18
  19 #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
  20   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
  21 #define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
  22   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
  23
  24 #define SET_SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
  25         li     x1, SV_REMAP_CSR( reg0, shape0, reg1, shape1, reg2, shape2); \
  26         csrrw  x0, 0x4f7, x1
  27
  28 #define SET_SV_SHAPE0_CSR(xd, yd, zd, offs, permute) \
  29         li     x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \
  30         csrrw  x0, 0x4f8, x1
  31
  32 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
  33         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
  34         csrrw  x0, 0x4c0, x1
  35
  36 #define SET_SV_CSR2( type, regkey, elwidth, regidx, isvec) \
  37         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
  38         csrrw  x0, 0x4c1, x1
  39
  40 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
  41         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
  42         csrrw  x0, 0x4c8, x1
  43
  44 #define SET_SV_2CSRS( c1, c2 ) \
  45         li     x1, c1 | ((c2)<<16U); \
  46         csrrw  x0, 0x4c0, x1
  47
  48 #define SET_SV_3CSRS( c1, c2 , c3 ) \
  49         li     x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
  50         csrrw  x0, 0x4c0, x1
  51
  52 #define SET_SV_2PREDCSRS( c1, c2 ) \
  53         li     x1, c1 | ((c2)<<16U); \
  54         csrrw  x0, 0x4c8, x1
  55
  56 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
  57 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
  58
  59 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
  60 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
  61
  62 #define SV_LD_DATA( reg, from, offs ) \
  63         la      x1, from; \
  64         lw      reg, offs(x1)
  65
  66 #define SV_LDD_DATA( reg, from, offs ) \
  67         la      x1, from; \
  68         ld      reg, offs(x1)
  69
  70 #define SV_FLD_DATA( reg, from, offs ) \
  71         la      x1, from; \
  72         fld     reg, offs(x1)
  73
  74 #define SV_FLW_DATA( reg, from, offs ) \
  75         la      x1, from; \
  76         flw     reg, offs(x1)
  77
  78 #define TEST_SV_IMMW( reg, imm ) \
  79         li      t6, MASK_XLEN(imm) ; \
  80         bne     reg, t6, fail;
  81
  82 #define TEST_SV_IMM( reg, imm ) \
  83         li      t6, ((imm) & 0xffffffffffffffff); \
  84         bne     reg, t6, fail;
  85
  86 #define TEST_SV_FD( flags, freg, from, offs ) \
  87         fsflags x2, x0; \
  88         li      x1, flags; \
  89         bne     x2, x1, fail; \
  90         la      x1, from; \
  91         ld      x1, offs(x1); \
  92         fmv.x.d x2, freg; \
  93         bne     x2, x1, fail;
  94
  95 #define TEST_SV_FW( flags, freg, from, offs ) \
  96         fsflags x2, x0; \
  97         li      x1, flags; \
  98         bne     x2, x1, fail; \
  99         la      x1, from; \
 100         lw      x1, offs(x1); \
 101         fmv.x.s x2, freg; \
 102         bne     x2, x1, fail;
 103
 104 #define SV_W_DFLT 0
 105 #define SV_W_8BIT 1
 106 #define SV_W_16BIT 2
 107 #define SV_W_32BIT 3