isa/macros/simplev/sv_test_macros.h

   1 #define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
   2
   3 #define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
   4   (reg0 | (reg1<<8) | (reg2<<8) | \
   5    (shape0<<24) | (shape0<<26) | (shape0<<28))
   6
   7 #define SV_SHAPE_PERM_XYZ 0
   8 #define SV_SHAPE_PERM_XZY 1
   9 #define SV_SHAPE_PERM_YXZ 2
  10 #define SV_SHAPE_PERM_YZX 3
  11 #define SV_SHAPE_PERM_ZXY 4
  12 #define SV_SHAPE_PERM_ZYX 5
  13
  14 #define SV_SHAPE_CSR(xd, yd, zd, offs, perm) \
  15   ((xd-1) | ((yd-1)<<8) | ((zd-1)<<16) | (perm<<24) | \
  16    ((offs&0x1)<<7) | ((offs&0x2)<<14) | ((offs&0x4)<<21) )
  17
  18
  19 #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
  20   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
  21 #define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
  22   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
  23
  24 #define SET_SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
  25         li     x1, SV_REMAP_CSR( reg0, shape0, reg1, shape1, reg2, shape2); \
  26         csrrw  x0, 0x4f7, x1
  27
  28 #define SET_SV_SHAPE0_CSR(xd, yd, zd, offs, permute) \
  29         li     x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \
  30         csrrw  x0, 0x4f8, x1
  31
  32 // series of macros that set one, two or three register (or predicate)
  33 // key-value table entries that alter the behaviour of the registers
  34 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
  35         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
  36         csrrw  x0, 0x4c0, x1
  37
  38 #define SET_SV_CSR2( type, regkey, elwidth, regidx, isvec) \
  39         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
  40         csrrw  x0, 0x4c1, x1
  41
  42 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
  43         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
  44         csrrw  x0, 0x4c8, x1
  45
  46 #define SET_SV_2CSRS( c1, c2 ) \
  47         li     x1, c1 | ((c2)<<16U); \
  48         csrrw  x0, 0x4c0, x1
  49
  50 #define SET_SV_3CSRS( c1, c2 , c3 ) \
  51         li     x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
  52         csrrw  x0, 0x4c0, x1
  53
  54 #define SET_SV_2PREDCSRS( c1, c2 ) \
  55         li     x1, c1 | ((c2)<<16U); \
  56         csrrw  x0, 0x4c8, x1
  57
  58 // clears the 2 CSRs set above
  59 #define CLR_SV_CSRS( ) csrrwi   x0, 0x4c0, 0xf;
  60 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
  61
  62 // set maximum vector length.
  63 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
  64
  65 // set actual vector length: normally that would
  66 // be vl = xN = min(mvl, min(vl, xN) however we
  67 // pass in x0 here.
  68 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
  69
  70 #define SV_LD_DATA( reg, from, offs ) \
  71         la      x1, from; \
  72         lw      reg, offs(x1)
  73
  74 #define SV_LDD_DATA( reg, from, offs ) \
  75         la      x1, from; \
  76         ld      reg, offs(x1)
  77
  78 #define SV_FLD_DATA( reg, from, offs ) \
  79         la      x1, from; \
  80         fld     reg, offs(x1)
  81
  82 #define SV_FLW_DATA( reg, from, offs ) \
  83         la      x1, from; \
  84         flw     reg, offs(x1)
  85
  86 #define TEST_SV_IMMW( reg, imm ) \
  87         li      t6, MASK_XLEN(imm) ; \
  88         bne     reg, t6, fail;
  89
  90 #define TEST_SV_IMM( reg, imm ) \
  91         li      t6, ((imm) & 0xffffffffffffffff); \
  92         bne     reg, t6, fail;
  93
  94 #define TEST_SV_FD( flags, freg, from, offs ) \
  95         fsflags x2, x0; \
  96         li      x1, flags; \
  97         bne     x2, x1, fail; \
  98         la      x1, from; \
  99         ld      x1, offs(x1); \
 100         fmv.x.d x2, freg; \
 101         bne     x2, x1, fail;
 102
 103 #define TEST_SV_FW( flags, freg, from, offs ) \
 104         fsflags x2, x0; \
 105         li      x1, flags; \
 106         bne     x2, x1, fail; \
 107         la      x1, from; \
 108         lw      x1, offs(x1); \
 109         fmv.x.s x2, freg; \
 110         bne     x2, x1, fail;
 111
 112 #define SV_ELWIDTH_NONLOAD_TEST(code, load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
 113                  expect1, expect2, expect3 )                                                                            \
 114         SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3,              \
 115                          expect1, expect2, expect3, code x28, x15, x12)                                                 \
 116
 117 #define SV_ELWIDTH_TEST(load_instruction, testdata, elwidth, vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
 118                          expect1, expect2, expect3, code... )                   \
 119                                                                        \
 120         load_instruction( x12, testdata   , 0);                             \
 121         load_instruction( x13, testdata+elwidth , 0);                             \
 122         load_instruction( x14, testdata+elwidth*2, 0);                             \
 123         load_instruction( x15, testdata+elwidth*3, 0);                             \
 124         load_instruction( x16, testdata+elwidth*4, 0);                             \
 125         load_instruction( x17, testdata++elwidth*5, 0);                             \
 126                                                                                \
 127         li x28, 0xa5a5a5a5a5a5a5a5;                                     \
 128         li x29, 0xa5a5a5a5a5a5a5a5;                                     \
 129         li x30, 0xa5a5a5a5a5a5a5a5;                                     \
 130                                                                                \
 131         SET_SV_MVL( vl );                                              \
 132         SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1),            \
 133                       SV_REG_CSR( 1, 12, wid2, 12, isvec2),            \
 134                       SV_REG_CSR( 1, 28, wid3, 28, isvec3));           \
 135         SET_SV_VL( vl );                                               \
 136                                                                        \
 137         code;                                          \
 138                                                                        \
 139         CLR_SV_CSRS();                                                         \
 140         SET_SV_VL( 1);                                                 \
 141         SET_SV_MVL( 1);                                                \
 142                                                                        \
 143         TEST_SV_IMM( x28, expect1 );                                   \
 144         TEST_SV_IMM( x29, expect2 );                                   \
 145         TEST_SV_IMM( x30, expect3 );                                   \
 146
 147 #define SV_W_DFLT 0
 148 #define SV_W_8BIT 1
 149 #define SV_W_16BIT 2
 150 #define SV_W_32BIT 3