isa/macros/vector/test_macros.h

   1 #ifndef __TEST_MACROS_VECTOR_H
   2 #define __TEST_MACROS_VECTOR_H
   3
   4 #undef EXTRA_INIT
   5 #define EXTRA_INIT RVTEST_VEC_ENABLE
   6
   7 #-----------------------------------------------------------------------
   8 # Helper macros
   9 #-----------------------------------------------------------------------
  10
  11 #define TEST_CASE( testnum, testreg, correctval, code... ) \
  12   TEST_CASE_NREG( testnum, 32, 32, testreg, correctval, code )
  13
  14 # We use j fail, because for some cases branches are not enough to jump to fail
  15
  16 #define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
  17 test_ ## testnum: \
  18   vsetcfg nxreg,nfreg; \
  19   li a3,2048; \
  20   vsetvl a3,a3; \
  21   lui a0,%hi(vtcode ## testnum ); \
  22   vf %lo(vtcode ## testnum )(a0); \
  23   la a4,dst; \
  24   vsd v ## testreg, a4; \
  25   fence; \
  26   li a1,correctval; \
  27   li a2,0; \
  28   li x28, testnum; \
  29 test_loop ## testnum: \
  30   ld a0,0(a4); \
  31   beq a0,a1,skip ## testnum; \
  32   j fail; \
  33 skip ## testnum : \
  34   addi a4,a4,8; \
  35   addi a2,a2,1; \
  36   bne a2,a3,test_loop ## testnum; \
  37   j next ## testnum; \
  38 vtcode ## testnum : \
  39   code; \
  40   stop; \
  41 next ## testnum :
  42
  43 # We use a macro hack to simpify code generation for various numbers
  44 # of bubble cycles.
  45
  46 #define TEST_INSERT_NOPS_0
  47 #define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
  48 #define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
  49 #define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
  50 #define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
  51 #define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
  52 #define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
  53 #define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
  54 #define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
  55 #define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
  56 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
  57
  58
  59 #-----------------------------------------------------------------------
  60 # RV64UI MACROS
  61 #-----------------------------------------------------------------------
  62
  63 #-----------------------------------------------------------------------
  64 # Tests for instructions with immediate operand
  65 #-----------------------------------------------------------------------
  66
  67 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
  68     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  69       li  x1, val1; \
  70       inst x3, x1, imm; \
  71     )
  72
  73 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
  74     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  75       li  x1, val1; \
  76       inst x1, x1, imm; \
  77     )
  78
  79 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  80     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
  81       li  x1, val1; \
  82       inst x3, x1, imm; \
  83       TEST_INSERT_NOPS_ ## nop_cycles \
  84       addi  x4, x3, 0; \
  85     )
  86
  87 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  88     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  89       li  x1, val1; \
  90       TEST_INSERT_NOPS_ ## nop_cycles \
  91       inst x3, x1, imm; \
  92     )
  93
  94 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
  95     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  96       inst x1, x0, imm; \
  97     )
  98
  99 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
 100     TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
 101       li  x1, val1; \
 102       inst x0, x1, imm; \
 103     )
 104
 105 #-----------------------------------------------------------------------
 106 # Tests for an instruction with register operands
 107 #-----------------------------------------------------------------------
 108
 109 #define TEST_R_OP( testnum, inst, result, val1 ) \
 110     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 111       li  x1, val1; \
 112       inst x3, x1; \
 113     )
 114
 115 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
 116     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 117       li  x1, val1; \
 118       inst x1, x1; \
 119     )
 120
 121 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
 122     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 123       li  x1, val1; \
 124       inst x3, x1; \
 125       TEST_INSERT_NOPS_ ## nop_cycles \
 126       addi  x4, x3, 0; \
 127     )
 128
 129 #-----------------------------------------------------------------------
 130 # Tests for an instruction with register-register operands
 131 #-----------------------------------------------------------------------
 132
 133 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
 134     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 135       li  x1, val1; \
 136       li  x2, val2; \
 137       inst x3, x1, x2; \
 138     )
 139
 140 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
 141     TEST_CASE_NREG( testnum, 3, 0, x1, result, \
 142       li  x1, val1; \
 143       li  x2, val2; \
 144       inst x1, x1, x2; \
 145     )
 146
 147 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
 148     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 149       li  x1, val1; \
 150       li  x2, val2; \
 151       inst x2, x1, x2; \
 152     )
 153
 154 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
 155     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 156       li  x1, val1; \
 157       inst x1, x1, x1; \
 158     )
 159
 160 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
 161     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 162       li  x1, val1; \
 163       li  x2, val2; \
 164       inst x3, x1, x2; \
 165       TEST_INSERT_NOPS_ ## nop_cycles \
 166       addi  x4, x3, 0; \
 167     )
 168
 169 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 170     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 171       li  x1, val1; \
 172       TEST_INSERT_NOPS_ ## src1_nops \
 173       li  x2, val2; \
 174       TEST_INSERT_NOPS_ ## src2_nops \
 175       inst x3, x1, x2; \
 176     )
 177
 178 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 179     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 180       li  x2, val2; \
 181       TEST_INSERT_NOPS_ ## src1_nops \
 182       li  x1, val1; \
 183       TEST_INSERT_NOPS_ ## src2_nops \
 184       inst x3, x1, x2; \
 185     )
 186
 187 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
 188     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 189       li x1, val; \
 190       inst x2, x0, x1; \
 191     )
 192
 193 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
 194     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 195       li x1, val; \
 196       inst x2, x1, x0; \
 197     )
 198
 199 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
 200     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 201       inst x1, x0, x0; \
 202     )
 203
 204 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
 205     TEST_CASE_NREG( testnum, 3, 0, x0, 0, \
 206       li x1, val1; \
 207       li x2, val2; \
 208       inst x0, x1, x2; \
 209     )
 210
 211
 212 #-----------------------------------------------------------------------
 213 # RV64UF MACROS
 214 #-----------------------------------------------------------------------
 215
 216 #-----------------------------------------------------------------------
 217 # Tests floating-point instructions
 218 #-----------------------------------------------------------------------
 219
 220 #define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 221 test_ ## testnum: \
 222   vsetcfg nxreg,nfreg; \
 223   li a3,2048; \
 224   vsetvl a3,a3; \
 225   la  a5, test_ ## testnum ## _data ;\
 226   vflstw vf0, a5, x0; \
 227   addi a5,a5,4; \
 228   vflstw vf1, a5, x0; \
 229   addi a5,a5,4; \
 230   vflstw vf2, a5, x0; \
 231   addi a5,a5,4; \
 232   lui a0,%hi(vtcode ## testnum ); \
 233   vf %lo(vtcode ## testnum )(a0); \
 234   la a4,dst; \
 235   vsw vx1, a4; \
 236   fence; \
 237   lw  a1, 0(a5); \
 238   li a2, 0; \
 239   li x28, testnum; \
 240 test_loop ## testnum: \
 241   lw a0,0(a4); \
 242   beq a0,a1,skip ## testnum; \
 243   j fail; \
 244 skip ## testnum : \
 245   addi a4,a4,4; \
 246   addi a2,a2,1; \
 247   bne a2,a3,test_loop ## testnum; \
 248   b 1f; \
 249 vtcode ## testnum : \
 250   code; \
 251   stop; \
 252   .align 2; \
 253   test_ ## testnum ## _data: \
 254   .float val1; \
 255   .float val2; \
 256   .float val3; \
 257   .result; \
 258 1:
 259
 260 #define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 261 test_ ## testnum: \
 262   vsetcfg nxreg,nfreg; \
 263   li a3,2048; \
 264   vsetvl a3,a3; \
 265   la  a5, test_ ## testnum ## _data ;\
 266   vflstd vf0, a5, x0; \
 267   addi a5,a5,8; \
 268   vflstd vf1, a5, x0; \
 269   addi a5,a5,8; \
 270   vflstd vf2, a5, x0; \
 271   addi a5,a5,8; \
 272   lui a0,%hi(vtcode ## testnum ); \
 273   vf %lo(vtcode ## testnum )(a0); \
 274   la a4,dst; \
 275   vsd vx1, a4; \
 276   fence; \
 277   ld  a1, 0(a5); \
 278   li a2, 0; \
 279   li x28, testnum; \
 280 test_loop ## testnum: \
 281   ld a0,0(a4); \
 282   beq a0,a1,skip ## testnum; \
 283   j fail; \
 284 skip ## testnum : \
 285   addi a4,a4,8; \
 286   addi a2,a2,1; \
 287   bne a2,a3,test_loop ## testnum; \
 288   b 1f; \
 289 vtcode ## testnum : \
 290   code; \
 291   stop; \
 292   .align 3; \
 293   test_ ## testnum ## _data: \
 294   .double val1; \
 295   .double val2; \
 296   .double val3; \
 297   .result; \
 298 1:
 299
 300 #define TEST_FCVT_S_D( testnum, result, val1 ) \
 301   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, 0.0, 0.0, \
 302                     fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d x1, f3)
 303
 304 #define TEST_FCVT_D_S( testnum, result, val1 ) \
 305   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
 306                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s x1, f3)
 307
 308 #define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
 309   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
 310                     inst f3, f0, f1; fmv.x.s x1, f3)
 311
 312 #define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
 313   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
 314                     inst f3, f0, f1; fmv.x.d x1, f3)
 315
 316 #define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
 317   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
 318                     inst f3, f0, f1, f2; fmv.x.s x1, f3)
 319
 320 #define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
 321   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
 322                     inst f3, f0, f1, f2; fmv.x.d x1, f3)
 323
 324 #define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
 325   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
 326                     inst x1, f0, rm)
 327
 328 #define TEST_FP_INT_OP_D( testnum, inst, result, val1, rm ) \
 329   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, 0.0, 0.0, \
 330                     inst x1, f0, rm)
 331
 332 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
 333   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, val2, 0.0, \
 334                     inst x1, f0, f1)
 335
 336 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
 337   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, val2, 0.0, \
 338                     inst x1, f0, f1)
 339
 340 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 341 test_ ## testnum: \
 342   vsetcfg 2,1; \
 343   li a3,2048; \
 344   vsetvl a3,a3; \
 345   lui a0,%hi(vtcode ## testnum ); \
 346   vf %lo(vtcode ## testnum )(a0); \
 347   la a4,dst; \
 348   vsw vx1, a4; \
 349   fence; \
 350   la  a5, test_ ## testnum ## _data ;\
 351   lw  a1, 0(a5); \
 352   li a2, 0; \
 353   li x28, testnum; \
 354 test_loop ## testnum: \
 355   lw a0,0(a4); \
 356   beq a0,a1,skip ## testnum; \
 357   j fail; \
 358 skip ## testnum : \
 359   addi a4,a4,4; \
 360   addi a2,a2,1; \
 361   bne a2,a3,test_loop ## testnum; \
 362   b 1f; \
 363 vtcode ## testnum : \
 364   li x1, val1; \
 365   inst f0, x1; \
 366   fmv.x.s x1, f0; \
 367   stop; \
 368   .align 2; \
 369   test_ ## testnum ## _data: \
 370   .float result; \
 371 1:
 372
 373 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 374 test_ ## testnum: \
 375   vsetcfg 2,1; \
 376   li a3,2048; \
 377   vsetvl a3,a3; \
 378   lui a0,%hi(vtcode ## testnum ); \
 379   vf %lo(vtcode ## testnum )(a0); \
 380   la a4,dst; \
 381   vsd vx1, a4; \
 382   fence; \
 383   la  a5, test_ ## testnum ## _data ;\
 384   ld  a1, 0(a5); \
 385   li a2, 0; \
 386   li x28, testnum; \
 387 test_loop ## testnum: \
 388   ld a0,0(a4); \
 389   beq a0,a1,skip ## testnum; \
 390   j fail; \
 391 skip ## testnum : \
 392   addi a4,a4,8; \
 393   addi a2,a2,1; \
 394   bne a2,a3,test_loop ## testnum; \
 395   b 1f; \
 396 vtcode ## testnum : \
 397   li x1, val1; \
 398   inst f0, x1; \
 399   fmv.x.d x1, f0; \
 400   stop; \
 401   .align 3; \
 402   test_ ## testnum ## _data: \
 403   .double result; \
 404 1:
 405
 406
 407 #-----------------------------------------------------------------------
 408 # RV64UV MACROS
 409 #-----------------------------------------------------------------------
 410
 411 #-----------------------------------------------------------------------
 412 # Test branch instructions
 413 #-----------------------------------------------------------------------
 414
 415 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2) \
 416     TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 417       li x1, val1; \
 418       li x2, val2; \
 419       add x3, x0, x0; \
 420       inst x1, x2, 2f; \
 421       addi x3, x3, 1; \
 422 1:    j 3f; \
 423       addi x3, x3, 4; \
 424 2:    inst x1, x2, 1b; \
 425       addi x3, x3, 2; \
 426 3: \
 427     )
 428
 429 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 430   TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 431     li  x1, val1; \
 432     li  x2, val2; \
 433     add x3, x0, x0; \
 434     inst x1, x2, 1f; \
 435     j 2f; \
 436 1:  addi x3, x3, 1; \
 437     j 3f; \
 438 2:  inst x1, x2, 1b; \
 439 3: \
 440                   )
 441
 442 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 443   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 444     add x3, x0, x0; \
 445     li  x4, 0; \
 446 1:  li  x1, val1; \
 447     TEST_INSERT_NOPS_ ## src1_nops \
 448     li  x2, val2; \
 449     TEST_INSERT_NOPS_ ## src2_nops \
 450     inst x1, x2, 2f; \
 451     addi  x4, x4, 1; \
 452     li  x5, 2; \
 453     bne x4, x5, 1b; \
 454     j 3f; \
 455 2:  add x3, x3, 1; \
 456 3:  \
 457   )
 458
 459 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 460   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 461     add x3, x0, x0; \
 462     li  x4, 0; \
 463 1:  li  x2, val2; \
 464     TEST_INSERT_NOPS_ ## src1_nops \
 465     li  x1, val1; \
 466     TEST_INSERT_NOPS_ ## src2_nops \
 467     inst x1, x2, 2f; \
 468     addi  x4, x4, 1; \
 469     li  x5, 2; \
 470     bne x4, x4, 1b; \
 471     j 3f; \
 472 2:  add x3, x3, 1; \
 473 3: \
 474                   )
 475
 476 #define TEST_BR2_DIVERGED_ODD_EVEN( testnum, inst, n, result, code...)   \
 477   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 478     utidx x1; \
 479     andi x2, x1, 1;\
 480     add x3, x0, x0; \
 481     li x4, n; \
 482 1: \
 483     beq x0, x2, 2f; \
 484     code; \
 485     j 3f; \
 486 2: \
 487     code; \
 488 3: \
 489     addi x4, x4, -1; \
 490     bne x4, x0, 1b; \
 491                   )
 492
 493 #define TEST_BR2_DIVERGED_FULL12( testnum, inst, n, result, code... )    \
 494   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 495     utidx x1; \
 496     sltiu x2, x1, 1; \
 497     add x3, x0, x0; \
 498     li x4, n; \
 499 1: \
 500     inst x2, x4, 2f; \
 501     addi x1, x1, -1; \
 502     sltiu x2, x1, 1; \
 503     j 1b; \
 504 2: \
 505     code; \
 506                  )
 507
 508 #define TEST_BR2_DIVERGED_FULL21( testnum, inst, n, result, code... )    \
 509   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 510     utidx x1; \
 511     sltiu x2, x1, 1; \
 512     add x3, x0, x0; \
 513     li x4, n; \
 514 1: \
 515     inst x4, x2, 2f; \
 516     addi x1, x1, -1; \
 517     sltiu x2, x1, 1; \
 518     j 1b; \
 519 2: \
 520     code; \
 521                  )
 522
 523 #define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
 524 test_ ## testnum: \
 525   vsetcfg nxreg,nfreg; \
 526   li a3,2048; \
 527   vsetvl a3,a3; \
 528   lui a0,%hi(vtcode ## testnum ); \
 529   vf %lo(vtcode ## testnum )(a0); \
 530   la a4,dst; \
 531   fence; \
 532   li a1,correctval; \
 533   li a2,0; \
 534   li x28, testnum; \
 535 test_loop ## testnum: \
 536   ld a0,0(a4); \
 537   beq a0,a1,skip ## testnum; \
 538   j fail; \
 539 skip ## testnum : \
 540   addi a4,a4,8; \
 541   addi a2,a2,1; \
 542   bne a2,a3,test_loop ## testnum; \
 543   j next ## testnum; \
 544 vtcode ## testnum : \
 545   code; \
 546   stop; \
 547 next ## testnum :
 548
 549 #define TEST_BR2_DIVERGED_MEM_FULL12( testnum, inst, n) \
 550   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 551     utidx x5; \
 552     slli x5, x5, 3; \
 553     la x6, dst; \
 554     add x5, x5, x6; \
 555     sd x0, 0(x5); \
 556     utidx x1; \
 557     sltiu x2, x1, 1; \
 558     li x4, n; \
 559 1: \
 560     inst x2, x4, 2f; \
 561     addi x1, x1, -1; \
 562     sltiu x2, x1, 1; \
 563     j 1b; \
 564 2: \
 565     ld x3, 0(x5); \
 566     addi x3, x3, 1; \
 567     sd x3, 0(x5); \
 568                  )
 569
 570 #define TEST_BR2_DIVERGED_MEM_FULL21( testnum, inst, n) \
 571   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 572     utidx x5; \
 573     slli x5, x5, 3; \
 574     la x6, dst; \
 575     add x5, x5, x6; \
 576     sd x0, 0(x5); \
 577     utidx x1; \
 578     sltiu x2, x1, 1; \
 579     li x4, n; \
 580 1: \
 581     inst x4, x2, 2f; \
 582     addi x1, x1, -1; \
 583     sltiu x2, x1, 1; \
 584     j 1b; \
 585 2: \
 586     ld x3, 0(x5); \
 587     addi x3, x3, 1; \
 588     sd x3, 0(x5); \
 589                  )
 590
 591 #-----------------------------------------------------------------------
 592 # Pass and fail code (assumes test num is in x28)
 593 #-----------------------------------------------------------------------
 594
 595 #define TEST_PASSFAIL \
 596         bne x0, x28, pass; \
 597 fail: \
 598         RVTEST_FAIL \
 599 pass: \
 600         RVTEST_PASS \
 601
 602
 603 #-----------------------------------------------------------------------
 604 # Test data section
 605 #-----------------------------------------------------------------------
 606
 607 #define TEST_DATA \
 608         .data; \
 609         .align 3; \
 610 dst: \
 611         .skip 16384; \
 612
 613 #endif