a97ffe7d9b0ff05ecfe7c46ae3f92f934caaa348
[riscv-tests.git] / isa / macros / vector / test_macros.h
1 // See LICENSE for license details.
2
3 #ifndef __TEST_MACROS_VECTOR_H
4 #define __TEST_MACROS_VECTOR_H
5
6 #undef EXTRA_INIT
7 #define EXTRA_INIT RVTEST_VEC_ENABLE
8
9 #-----------------------------------------------------------------------
10 # Helper macros
11 #-----------------------------------------------------------------------
12
13 #define TEST_CASE( testnum, testreg, correctval, code... ) \
14 TEST_CASE_NREG( testnum, 32, 32, testreg, correctval, code )
15
16 # We use j fail, because for some cases branches are not enough to jump to fail
17
18 #define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
19 test_ ## testnum: \
20 vsetcfg nxreg,nfreg; \
21 li a3,2048; \
22 vsetvl a3,a3; \
23 lui a0,%hi(vtcode ## testnum ); \
24 vf %lo(vtcode ## testnum )(a0); \
25 la a4,dst; \
26 vsd v ## testreg, a4; \
27 fence; \
28 li a1,correctval; \
29 li a2,0; \
30 li TESTNUM, testnum; \
31 test_loop ## testnum: \
32 ld a0,0(a4); \
33 beq a0,a1,skip ## testnum; \
34 j fail; \
35 skip ## testnum : \
36 addi a4,a4,8; \
37 addi a2,a2,1; \
38 bne a2,a3,test_loop ## testnum; \
39 j next ## testnum; \
40 vtcode ## testnum : \
41 code; \
42 stop; \
43 next ## testnum :
44
45 # We use a macro hack to simpify code generation for various numbers
46 # of bubble cycles.
47
48 #define TEST_INSERT_NOPS_0
49 #define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
50 #define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
51 #define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
52 #define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
53 #define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
54 #define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
55 #define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
56 #define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
57 #define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
58 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
59
60
61 #-----------------------------------------------------------------------
62 # RV64UI MACROS
63 #-----------------------------------------------------------------------
64
65 #-----------------------------------------------------------------------
66 # Tests for instructions with immediate operand
67 #-----------------------------------------------------------------------
68
69 #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
70
71 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
72 TEST_CASE_NREG( testnum, 4, 0, x3, result, \
73 li x1, val1; \
74 inst x3, x1, SEXT_IMM(imm); \
75 )
76
77 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
78 TEST_CASE_NREG( testnum, 2, 0, x1, result, \
79 li x1, val1; \
80 inst x1, x1, SEXT_IMM(imm); \
81 )
82
83 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
84 TEST_CASE_NREG( testnum, 5, 0, x4, result, \
85 li x1, val1; \
86 inst x3, x1, SEXT_IMM(imm); \
87 TEST_INSERT_NOPS_ ## nop_cycles \
88 addi x4, x3, 0; \
89 )
90
91 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
92 TEST_CASE_NREG( testnum, 4, 0, x3, result, \
93 li x1, val1; \
94 TEST_INSERT_NOPS_ ## nop_cycles \
95 inst x3, x1, SEXT_IMM(imm); \
96 )
97
98 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
99 TEST_CASE_NREG( testnum, 2, 0, x1, result, \
100 inst x1, x0, SEXT_IMM(imm); \
101 )
102
103 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
104 TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
105 li x1, val1; \
106 inst x0, x1, SEXT_IMM(imm); \
107 )
108
109 #-----------------------------------------------------------------------
110 # Tests for an instruction with register operands
111 #-----------------------------------------------------------------------
112
113 #define TEST_R_OP( testnum, inst, result, val1 ) \
114 TEST_CASE_NREG( testnum, 4, 0, x3, result, \
115 li x1, val1; \
116 inst x3, x1; \
117 )
118
119 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
120 TEST_CASE_NREG( testnum, 2, 0, x1, result, \
121 li x1, val1; \
122 inst x1, x1; \
123 )
124
125 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
126 TEST_CASE_NREG( testnum, 5, 0, x4, result, \
127 li x1, val1; \
128 inst x3, x1; \
129 TEST_INSERT_NOPS_ ## nop_cycles \
130 addi x4, x3, 0; \
131 )
132
133 #-----------------------------------------------------------------------
134 # Tests for an instruction with register-register operands
135 #-----------------------------------------------------------------------
136
137 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
138 TEST_CASE_NREG( testnum, 4, 0, x3, result, \
139 li x1, val1; \
140 li x2, val2; \
141 inst x3, x1, x2; \
142 )
143
144 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
145 TEST_CASE_NREG( testnum, 3, 0, x1, result, \
146 li x1, val1; \
147 li x2, val2; \
148 inst x1, x1, x2; \
149 )
150
151 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
152 TEST_CASE_NREG( testnum, 3, 0, x2, result, \
153 li x1, val1; \
154 li x2, val2; \
155 inst x2, x1, x2; \
156 )
157
158 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
159 TEST_CASE_NREG( testnum, 2, 0, x1, result, \
160 li x1, val1; \
161 inst x1, x1, x1; \
162 )
163
164 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
165 TEST_CASE_NREG( testnum, 5, 0, x4, result, \
166 li x1, val1; \
167 li x2, val2; \
168 inst x3, x1, x2; \
169 TEST_INSERT_NOPS_ ## nop_cycles \
170 addi x4, x3, 0; \
171 )
172
173 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
174 TEST_CASE_NREG( testnum, 4, 0, x3, result, \
175 li x1, val1; \
176 TEST_INSERT_NOPS_ ## src1_nops \
177 li x2, val2; \
178 TEST_INSERT_NOPS_ ## src2_nops \
179 inst x3, x1, x2; \
180 )
181
182 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
183 TEST_CASE_NREG( testnum, 4, 0, x3, result, \
184 li x2, val2; \
185 TEST_INSERT_NOPS_ ## src1_nops \
186 li x1, val1; \
187 TEST_INSERT_NOPS_ ## src2_nops \
188 inst x3, x1, x2; \
189 )
190
191 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
192 TEST_CASE_NREG( testnum, 3, 0, x2, result, \
193 li x1, val; \
194 inst x2, x0, x1; \
195 )
196
197 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
198 TEST_CASE_NREG( testnum, 3, 0, x2, result, \
199 li x1, val; \
200 inst x2, x1, x0; \
201 )
202
203 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
204 TEST_CASE_NREG( testnum, 2, 0, x1, result, \
205 inst x1, x0, x0; \
206 )
207
208 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
209 TEST_CASE_NREG( testnum, 3, 0, x0, 0, \
210 li x1, val1; \
211 li x2, val2; \
212 inst x0, x1, x2; \
213 )
214
215
216 #-----------------------------------------------------------------------
217 # RV64UF MACROS
218 #-----------------------------------------------------------------------
219
220 #-----------------------------------------------------------------------
221 # Tests floating-point instructions
222 #-----------------------------------------------------------------------
223
224 #define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
225 test_ ## testnum: \
226 vsetcfg nxreg,nfreg; \
227 li a3,2048; \
228 vsetvl a3,a3; \
229 la a5, test_ ## testnum ## _data ;\
230 vflstw vf0, a5, x0; \
231 addi a5,a5,4; \
232 vflstw vf1, a5, x0; \
233 addi a5,a5,4; \
234 vflstw vf2, a5, x0; \
235 addi a5,a5,4; \
236 lui a0,%hi(vtcode ## testnum ); \
237 vf %lo(vtcode ## testnum )(a0); \
238 la a4,dst; \
239 vsw vx1, a4; \
240 fence; \
241 lw a1, 0(a5); \
242 li a2, 0; \
243 li TESTNUM, testnum; \
244 test_loop ## testnum: \
245 lw a0,0(a4); \
246 beq a0,a1,skip ## testnum; \
247 j fail; \
248 skip ## testnum : \
249 addi a4,a4,4; \
250 addi a2,a2,1; \
251 bne a2,a3,test_loop ## testnum; \
252 j 1f; \
253 vtcode ## testnum : \
254 code; \
255 stop; \
256 .align 2; \
257 test_ ## testnum ## _data: \
258 .float val1; \
259 .float val2; \
260 .float val3; \
261 .result; \
262 1:
263
264 #define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
265 test_ ## testnum: \
266 vsetcfg nxreg,nfreg; \
267 li a3,2048; \
268 vsetvl a3,a3; \
269 la a5, test_ ## testnum ## _data ;\
270 vflstd vf0, a5, x0; \
271 addi a5,a5,8; \
272 vflstd vf1, a5, x0; \
273 addi a5,a5,8; \
274 vflstd vf2, a5, x0; \
275 addi a5,a5,8; \
276 lui a0,%hi(vtcode ## testnum ); \
277 vf %lo(vtcode ## testnum )(a0); \
278 la a4,dst; \
279 vsd vx1, a4; \
280 fence; \
281 ld a1, 0(a5); \
282 li a2, 0; \
283 li TESTNUM, testnum; \
284 test_loop ## testnum: \
285 ld a0,0(a4); \
286 beq a0,a1,skip ## testnum; \
287 j fail; \
288 skip ## testnum : \
289 addi a4,a4,8; \
290 addi a2,a2,1; \
291 bne a2,a3,test_loop ## testnum; \
292 j 1f; \
293 vtcode ## testnum : \
294 code; \
295 stop; \
296 .align 3; \
297 test_ ## testnum ## _data: \
298 .double val1; \
299 .double val2; \
300 .double val3; \
301 .result; \
302 1:
303
304 #define TEST_FCVT_S_D( testnum, result, val1 ) \
305 TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, 0.0, 0.0, \
306 fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d x1, f3)
307
308 #define TEST_FCVT_D_S( testnum, result, val1 ) \
309 TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
310 fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s x1, f3)
311
312 #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
313 TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
314 inst f3, f0, f1; fmv.x.s x1, f3)
315
316 #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
317 TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
318 inst f3, f0, f1; fmv.x.d x1, f3)
319
320 #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
321 TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
322 inst f3, f0, f1, f2; fmv.x.s x1, f3)
323
324 #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
325 TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
326 inst f3, f0, f1, f2; fmv.x.d x1, f3)
327
328 #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
329 TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
330 inst x1, f0, rm)
331
332 #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
333 TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, 0.0, 0.0, \
334 inst x1, f0, rm)
335
336 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
337 TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, val2, 0.0, \
338 inst x1, f0, f1)
339
340 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
341 TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, val2, 0.0, \
342 inst x1, f0, f1)
343
344 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
345 test_ ## testnum: \
346 vsetcfg 2,1; \
347 li a3,2048; \
348 vsetvl a3,a3; \
349 lui a0,%hi(vtcode ## testnum ); \
350 vf %lo(vtcode ## testnum )(a0); \
351 la a4,dst; \
352 vsw vx1, a4; \
353 fence; \
354 la a5, test_ ## testnum ## _data ;\
355 lw a1, 0(a5); \
356 li a2, 0; \
357 li TESTNUM, testnum; \
358 test_loop ## testnum: \
359 lw a0,0(a4); \
360 beq a0,a1,skip ## testnum; \
361 j fail; \
362 skip ## testnum : \
363 addi a4,a4,4; \
364 addi a2,a2,1; \
365 bne a2,a3,test_loop ## testnum; \
366 j 1f; \
367 vtcode ## testnum : \
368 li x1, val1; \
369 inst f0, x1; \
370 fmv.x.s x1, f0; \
371 stop; \
372 .align 2; \
373 test_ ## testnum ## _data: \
374 .float result; \
375 1:
376
377 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
378 test_ ## testnum: \
379 vsetcfg 2,1; \
380 li a3,2048; \
381 vsetvl a3,a3; \
382 lui a0,%hi(vtcode ## testnum ); \
383 vf %lo(vtcode ## testnum )(a0); \
384 la a4,dst; \
385 vsd vx1, a4; \
386 fence; \
387 la a5, test_ ## testnum ## _data ;\
388 ld a1, 0(a5); \
389 li a2, 0; \
390 li TESTNUM, testnum; \
391 test_loop ## testnum: \
392 ld a0,0(a4); \
393 beq a0,a1,skip ## testnum; \
394 j fail; \
395 skip ## testnum : \
396 addi a4,a4,8; \
397 addi a2,a2,1; \
398 bne a2,a3,test_loop ## testnum; \
399 j 1f; \
400 vtcode ## testnum : \
401 li x1, val1; \
402 inst f0, x1; \
403 fmv.x.d x1, f0; \
404 stop; \
405 .align 3; \
406 test_ ## testnum ## _data: \
407 .double result; \
408 1:
409
410
411 #-----------------------------------------------------------------------
412 # RV64UV MACROS
413 #-----------------------------------------------------------------------
414
415 #-----------------------------------------------------------------------
416 # Test branch instructions
417 #-----------------------------------------------------------------------
418
419 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2) \
420 TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
421 li x1, val1; \
422 li x2, val2; \
423 add x3, x0, x0; \
424 inst x1, x2, 2f; \
425 addi x3, x3, 1; \
426 1: j 3f; \
427 addi x3, x3, 4; \
428 2: inst x1, x2, 1b; \
429 addi x3, x3, 2; \
430 3: \
431 )
432
433 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
434 TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
435 li x1, val1; \
436 li x2, val2; \
437 add x3, x0, x0; \
438 inst x1, x2, 1f; \
439 j 2f; \
440 1: addi x3, x3, 1; \
441 j 3f; \
442 2: inst x1, x2, 1b; \
443 3: \
444 )
445
446 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
447 TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
448 add x3, x0, x0; \
449 li x4, 0; \
450 1: li x1, val1; \
451 TEST_INSERT_NOPS_ ## src1_nops \
452 li x2, val2; \
453 TEST_INSERT_NOPS_ ## src2_nops \
454 inst x1, x2, 2f; \
455 addi x4, x4, 1; \
456 li x5, 2; \
457 bne x4, x5, 1b; \
458 j 3f; \
459 2: add x3, x3, 1; \
460 3: \
461 )
462
463 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
464 TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
465 add x3, x0, x0; \
466 li x4, 0; \
467 1: li x2, val2; \
468 TEST_INSERT_NOPS_ ## src1_nops \
469 li x1, val1; \
470 TEST_INSERT_NOPS_ ## src2_nops \
471 inst x1, x2, 2f; \
472 addi x4, x4, 1; \
473 li x5, 2; \
474 bne x4, x4, 1b; \
475 j 3f; \
476 2: add x3, x3, 1; \
477 3: \
478 )
479
480 #define TEST_BR2_DIVERGED_ODD_EVEN( testnum, inst, n, result, code...) \
481 TEST_CASE_NREG( testnum, 5, 0, x3, result, \
482 utidx x1; \
483 andi x2, x1, 1;\
484 add x3, x0, x0; \
485 li x4, n; \
486 1: \
487 beq x0, x2, 2f; \
488 code; \
489 j 3f; \
490 2: \
491 code; \
492 3: \
493 addi x4, x4, -1; \
494 bne x4, x0, 1b; \
495 )
496
497 #define TEST_BR2_DIVERGED_FULL12( testnum, inst, n, result, code... ) \
498 TEST_CASE_NREG( testnum, 5, 0, x3, result, \
499 utidx x1; \
500 sltiu x2, x1, 1; \
501 add x3, x0, x0; \
502 li x4, n; \
503 1: \
504 inst x2, x4, 2f; \
505 addi x1, x1, -1; \
506 sltiu x2, x1, 1; \
507 j 1b; \
508 2: \
509 code; \
510 )
511
512 #define TEST_BR2_DIVERGED_FULL21( testnum, inst, n, result, code... ) \
513 TEST_CASE_NREG( testnum, 5, 0, x3, result, \
514 utidx x1; \
515 sltiu x2, x1, 1; \
516 add x3, x0, x0; \
517 li x4, n; \
518 1: \
519 inst x4, x2, 2f; \
520 addi x1, x1, -1; \
521 sltiu x2, x1, 1; \
522 j 1b; \
523 2: \
524 code; \
525 )
526
527 #define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
528 test_ ## testnum: \
529 vsetcfg nxreg,nfreg; \
530 li a3,2048; \
531 vsetvl a3,a3; \
532 lui a0,%hi(vtcode ## testnum ); \
533 vf %lo(vtcode ## testnum )(a0); \
534 la a4,dst; \
535 fence; \
536 li a1,correctval; \
537 li a2,0; \
538 li TESTNUM, testnum; \
539 test_loop ## testnum: \
540 ld a0,0(a4); \
541 beq a0,a1,skip ## testnum; \
542 j fail; \
543 skip ## testnum : \
544 addi a4,a4,8; \
545 addi a2,a2,1; \
546 bne a2,a3,test_loop ## testnum; \
547 j next ## testnum; \
548 vtcode ## testnum : \
549 code; \
550 stop; \
551 next ## testnum :
552
553 #define TEST_BR2_DIVERGED_MEM_FULL12( testnum, inst, n) \
554 TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
555 utidx x5; \
556 slli x5, x5, 3; \
557 la x6, dst; \
558 add x5, x5, x6; \
559 sd x0, 0(x5); \
560 utidx x1; \
561 sltiu x2, x1, 1; \
562 li x4, n; \
563 1: \
564 inst x2, x4, 2f; \
565 addi x1, x1, -1; \
566 sltiu x2, x1, 1; \
567 j 1b; \
568 2: \
569 ld x3, 0(x5); \
570 addi x3, x3, 1; \
571 sd x3, 0(x5); \
572 )
573
574 #define TEST_BR2_DIVERGED_MEM_FULL21( testnum, inst, n) \
575 TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
576 utidx x5; \
577 slli x5, x5, 3; \
578 la x6, dst; \
579 add x5, x5, x6; \
580 sd x0, 0(x5); \
581 utidx x1; \
582 sltiu x2, x1, 1; \
583 li x4, n; \
584 1: \
585 inst x4, x2, 2f; \
586 addi x1, x1, -1; \
587 sltiu x2, x1, 1; \
588 j 1b; \
589 2: \
590 ld x3, 0(x5); \
591 addi x3, x3, 1; \
592 sd x3, 0(x5); \
593 )
594
595 #-----------------------------------------------------------------------
596 # Pass and fail code (assumes test num is in TESTNUM)
597 #-----------------------------------------------------------------------
598
599 #define TEST_PASSFAIL \
600 bne x0, TESTNUM, pass; \
601 fail: \
602 RVTEST_FAIL; \
603 pass: \
604 RVTEST_PASS \
605
606
607 #-----------------------------------------------------------------------
608 # Test data section
609 #-----------------------------------------------------------------------
610
611 #define TEST_DATA \
612 .data; \
613 .align 3; \
614 dst: \
615 .skip 16384; \
616
617 #endif