isa/macros/vector/test_macros.h

   1 #ifndef __TEST_MACROS_VECTOR_H
   2 #define __TEST_MACROS_VECTOR_H
   3
   4 #undef EXTRA_INIT
   5 #define EXTRA_INIT RVTEST_VEC_ENABLE
   6
   7 #-----------------------------------------------------------------------
   8 # Helper macros
   9 #-----------------------------------------------------------------------
  10
  11 #define TEST_CASE( testnum, testreg, correctval, code... ) \
  12   TEST_CASE_NREG( testnum, 32, 32, testreg, correctval, code )
  13
  14 # We use j fail, because for some cases branches are not enough to jump to fail
  15
  16 #define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
  17 test_ ## testnum: \
  18   vsetcfg nxreg,nfreg; \
  19   li a3,2048; \
  20   vsetvl a3,a3; \
  21   lui a0,%hi(vtcode ## testnum ); \
  22   vf %lo(vtcode ## testnum )(a0); \
  23   la a4,dst; \
  24   vsd v ## testreg, a4; \
  25   fence; \
  26   li a1,correctval; \
  27   li a2,0; \
  28   li TESTNUM, testnum; \
  29 test_loop ## testnum: \
  30   ld a0,0(a4); \
  31   beq a0,a1,skip ## testnum; \
  32   j fail; \
  33 skip ## testnum : \
  34   addi a4,a4,8; \
  35   addi a2,a2,1; \
  36   bne a2,a3,test_loop ## testnum; \
  37   j next ## testnum; \
  38 vtcode ## testnum : \
  39   code; \
  40   stop; \
  41 next ## testnum :
  42
  43 # We use a macro hack to simpify code generation for various numbers
  44 # of bubble cycles.
  45
  46 #define TEST_INSERT_NOPS_0
  47 #define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
  48 #define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
  49 #define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
  50 #define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
  51 #define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
  52 #define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
  53 #define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
  54 #define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
  55 #define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
  56 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
  57
  58
  59 #-----------------------------------------------------------------------
  60 # RV64UI MACROS
  61 #-----------------------------------------------------------------------
  62
  63 #-----------------------------------------------------------------------
  64 # Tests for instructions with immediate operand
  65 #-----------------------------------------------------------------------
  66
  67 #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
  68
  69 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
  70     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  71       li  x1, val1; \
  72       inst x3, x1, SEXT_IMM(imm); \
  73     )
  74
  75 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
  76     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  77       li  x1, val1; \
  78       inst x1, x1, SEXT_IMM(imm); \
  79     )
  80
  81 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  82     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
  83       li  x1, val1; \
  84       inst x3, x1, SEXT_IMM(imm); \
  85       TEST_INSERT_NOPS_ ## nop_cycles \
  86       addi  x4, x3, 0; \
  87     )
  88
  89 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  90     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  91       li  x1, val1; \
  92       TEST_INSERT_NOPS_ ## nop_cycles \
  93       inst x3, x1, SEXT_IMM(imm); \
  94     )
  95
  96 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
  97     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  98       inst x1, x0, SEXT_IMM(imm); \
  99     )
 100
 101 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
 102     TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
 103       li  x1, val1; \
 104       inst x0, x1, SEXT_IMM(imm); \
 105     )
 106
 107 #-----------------------------------------------------------------------
 108 # Tests for an instruction with register operands
 109 #-----------------------------------------------------------------------
 110
 111 #define TEST_R_OP( testnum, inst, result, val1 ) \
 112     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 113       li  x1, val1; \
 114       inst x3, x1; \
 115     )
 116
 117 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
 118     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 119       li  x1, val1; \
 120       inst x1, x1; \
 121     )
 122
 123 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
 124     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 125       li  x1, val1; \
 126       inst x3, x1; \
 127       TEST_INSERT_NOPS_ ## nop_cycles \
 128       addi  x4, x3, 0; \
 129     )
 130
 131 #-----------------------------------------------------------------------
 132 # Tests for an instruction with register-register operands
 133 #-----------------------------------------------------------------------
 134
 135 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
 136     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 137       li  x1, val1; \
 138       li  x2, val2; \
 139       inst x3, x1, x2; \
 140     )
 141
 142 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
 143     TEST_CASE_NREG( testnum, 3, 0, x1, result, \
 144       li  x1, val1; \
 145       li  x2, val2; \
 146       inst x1, x1, x2; \
 147     )
 148
 149 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
 150     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 151       li  x1, val1; \
 152       li  x2, val2; \
 153       inst x2, x1, x2; \
 154     )
 155
 156 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
 157     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 158       li  x1, val1; \
 159       inst x1, x1, x1; \
 160     )
 161
 162 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
 163     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 164       li  x1, val1; \
 165       li  x2, val2; \
 166       inst x3, x1, x2; \
 167       TEST_INSERT_NOPS_ ## nop_cycles \
 168       addi  x4, x3, 0; \
 169     )
 170
 171 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 172     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 173       li  x1, val1; \
 174       TEST_INSERT_NOPS_ ## src1_nops \
 175       li  x2, val2; \
 176       TEST_INSERT_NOPS_ ## src2_nops \
 177       inst x3, x1, x2; \
 178     )
 179
 180 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 181     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 182       li  x2, val2; \
 183       TEST_INSERT_NOPS_ ## src1_nops \
 184       li  x1, val1; \
 185       TEST_INSERT_NOPS_ ## src2_nops \
 186       inst x3, x1, x2; \
 187     )
 188
 189 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
 190     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 191       li x1, val; \
 192       inst x2, x0, x1; \
 193     )
 194
 195 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
 196     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 197       li x1, val; \
 198       inst x2, x1, x0; \
 199     )
 200
 201 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
 202     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 203       inst x1, x0, x0; \
 204     )
 205
 206 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
 207     TEST_CASE_NREG( testnum, 3, 0, x0, 0, \
 208       li x1, val1; \
 209       li x2, val2; \
 210       inst x0, x1, x2; \
 211     )
 212
 213
 214 #-----------------------------------------------------------------------
 215 # RV64UF MACROS
 216 #-----------------------------------------------------------------------
 217
 218 #-----------------------------------------------------------------------
 219 # Tests floating-point instructions
 220 #-----------------------------------------------------------------------
 221
 222 #define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 223 test_ ## testnum: \
 224   vsetcfg nxreg,nfreg; \
 225   li a3,2048; \
 226   vsetvl a3,a3; \
 227   la  a5, test_ ## testnum ## _data ;\
 228   vflstw vf0, a5, x0; \
 229   addi a5,a5,4; \
 230   vflstw vf1, a5, x0; \
 231   addi a5,a5,4; \
 232   vflstw vf2, a5, x0; \
 233   addi a5,a5,4; \
 234   lui a0,%hi(vtcode ## testnum ); \
 235   vf %lo(vtcode ## testnum )(a0); \
 236   la a4,dst; \
 237   vsw vx1, a4; \
 238   fence; \
 239   lw  a1, 0(a5); \
 240   li a2, 0; \
 241   li TESTNUM, testnum; \
 242 test_loop ## testnum: \
 243   lw a0,0(a4); \
 244   beq a0,a1,skip ## testnum; \
 245   j fail; \
 246 skip ## testnum : \
 247   addi a4,a4,4; \
 248   addi a2,a2,1; \
 249   bne a2,a3,test_loop ## testnum; \
 250   b 1f; \
 251 vtcode ## testnum : \
 252   code; \
 253   stop; \
 254   .align 2; \
 255   test_ ## testnum ## _data: \
 256   .float val1; \
 257   .float val2; \
 258   .float val3; \
 259   .result; \
 260 1:
 261
 262 #define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 263 test_ ## testnum: \
 264   vsetcfg nxreg,nfreg; \
 265   li a3,2048; \
 266   vsetvl a3,a3; \
 267   la  a5, test_ ## testnum ## _data ;\
 268   vflstd vf0, a5, x0; \
 269   addi a5,a5,8; \
 270   vflstd vf1, a5, x0; \
 271   addi a5,a5,8; \
 272   vflstd vf2, a5, x0; \
 273   addi a5,a5,8; \
 274   lui a0,%hi(vtcode ## testnum ); \
 275   vf %lo(vtcode ## testnum )(a0); \
 276   la a4,dst; \
 277   vsd vx1, a4; \
 278   fence; \
 279   ld  a1, 0(a5); \
 280   li a2, 0; \
 281   li TESTNUM, testnum; \
 282 test_loop ## testnum: \
 283   ld a0,0(a4); \
 284   beq a0,a1,skip ## testnum; \
 285   j fail; \
 286 skip ## testnum : \
 287   addi a4,a4,8; \
 288   addi a2,a2,1; \
 289   bne a2,a3,test_loop ## testnum; \
 290   b 1f; \
 291 vtcode ## testnum : \
 292   code; \
 293   stop; \
 294   .align 3; \
 295   test_ ## testnum ## _data: \
 296   .double val1; \
 297   .double val2; \
 298   .double val3; \
 299   .result; \
 300 1:
 301
 302 #define TEST_FCVT_S_D( testnum, result, val1 ) \
 303   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, 0.0, 0.0, \
 304                     fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d x1, f3)
 305
 306 #define TEST_FCVT_D_S( testnum, result, val1 ) \
 307   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
 308                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s x1, f3)
 309
 310 #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
 311   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
 312                     inst f3, f0, f1; fmv.x.s x1, f3)
 313
 314 #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
 315   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
 316                     inst f3, f0, f1; fmv.x.d x1, f3)
 317
 318 #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
 319   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
 320                     inst f3, f0, f1, f2; fmv.x.s x1, f3)
 321
 322 #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
 323   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
 324                     inst f3, f0, f1, f2; fmv.x.d x1, f3)
 325
 326 #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
 327   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
 328                     inst x1, f0, rm)
 329
 330 #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
 331   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, 0.0, 0.0, \
 332                     inst x1, f0, rm)
 333
 334 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
 335   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, val2, 0.0, \
 336                     inst x1, f0, f1)
 337
 338 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
 339   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, val2, 0.0, \
 340                     inst x1, f0, f1)
 341
 342 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 343 test_ ## testnum: \
 344   vsetcfg 2,1; \
 345   li a3,2048; \
 346   vsetvl a3,a3; \
 347   lui a0,%hi(vtcode ## testnum ); \
 348   vf %lo(vtcode ## testnum )(a0); \
 349   la a4,dst; \
 350   vsw vx1, a4; \
 351   fence; \
 352   la  a5, test_ ## testnum ## _data ;\
 353   lw  a1, 0(a5); \
 354   li a2, 0; \
 355   li TESTNUM, testnum; \
 356 test_loop ## testnum: \
 357   lw a0,0(a4); \
 358   beq a0,a1,skip ## testnum; \
 359   j fail; \
 360 skip ## testnum : \
 361   addi a4,a4,4; \
 362   addi a2,a2,1; \
 363   bne a2,a3,test_loop ## testnum; \
 364   b 1f; \
 365 vtcode ## testnum : \
 366   li x1, val1; \
 367   inst f0, x1; \
 368   fmv.x.s x1, f0; \
 369   stop; \
 370   .align 2; \
 371   test_ ## testnum ## _data: \
 372   .float result; \
 373 1:
 374
 375 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 376 test_ ## testnum: \
 377   vsetcfg 2,1; \
 378   li a3,2048; \
 379   vsetvl a3,a3; \
 380   lui a0,%hi(vtcode ## testnum ); \
 381   vf %lo(vtcode ## testnum )(a0); \
 382   la a4,dst; \
 383   vsd vx1, a4; \
 384   fence; \
 385   la  a5, test_ ## testnum ## _data ;\
 386   ld  a1, 0(a5); \
 387   li a2, 0; \
 388   li TESTNUM, testnum; \
 389 test_loop ## testnum: \
 390   ld a0,0(a4); \
 391   beq a0,a1,skip ## testnum; \
 392   j fail; \
 393 skip ## testnum : \
 394   addi a4,a4,8; \
 395   addi a2,a2,1; \
 396   bne a2,a3,test_loop ## testnum; \
 397   b 1f; \
 398 vtcode ## testnum : \
 399   li x1, val1; \
 400   inst f0, x1; \
 401   fmv.x.d x1, f0; \
 402   stop; \
 403   .align 3; \
 404   test_ ## testnum ## _data: \
 405   .double result; \
 406 1:
 407
 408
 409 #-----------------------------------------------------------------------
 410 # RV64UV MACROS
 411 #-----------------------------------------------------------------------
 412
 413 #-----------------------------------------------------------------------
 414 # Test branch instructions
 415 #-----------------------------------------------------------------------
 416
 417 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2) \
 418     TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 419       li x1, val1; \
 420       li x2, val2; \
 421       add x3, x0, x0; \
 422       inst x1, x2, 2f; \
 423       addi x3, x3, 1; \
 424 1:    j 3f; \
 425       addi x3, x3, 4; \
 426 2:    inst x1, x2, 1b; \
 427       addi x3, x3, 2; \
 428 3: \
 429     )
 430
 431 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 432   TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 433     li  x1, val1; \
 434     li  x2, val2; \
 435     add x3, x0, x0; \
 436     inst x1, x2, 1f; \
 437     j 2f; \
 438 1:  addi x3, x3, 1; \
 439     j 3f; \
 440 2:  inst x1, x2, 1b; \
 441 3: \
 442                   )
 443
 444 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 445   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 446     add x3, x0, x0; \
 447     li  x4, 0; \
 448 1:  li  x1, val1; \
 449     TEST_INSERT_NOPS_ ## src1_nops \
 450     li  x2, val2; \
 451     TEST_INSERT_NOPS_ ## src2_nops \
 452     inst x1, x2, 2f; \
 453     addi  x4, x4, 1; \
 454     li  x5, 2; \
 455     bne x4, x5, 1b; \
 456     j 3f; \
 457 2:  add x3, x3, 1; \
 458 3:  \
 459   )
 460
 461 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 462   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 463     add x3, x0, x0; \
 464     li  x4, 0; \
 465 1:  li  x2, val2; \
 466     TEST_INSERT_NOPS_ ## src1_nops \
 467     li  x1, val1; \
 468     TEST_INSERT_NOPS_ ## src2_nops \
 469     inst x1, x2, 2f; \
 470     addi  x4, x4, 1; \
 471     li  x5, 2; \
 472     bne x4, x4, 1b; \
 473     j 3f; \
 474 2:  add x3, x3, 1; \
 475 3: \
 476                   )
 477
 478 #define TEST_BR2_DIVERGED_ODD_EVEN( testnum, inst, n, result, code...)   \
 479   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 480     utidx x1; \
 481     andi x2, x1, 1;\
 482     add x3, x0, x0; \
 483     li x4, n; \
 484 1: \
 485     beq x0, x2, 2f; \
 486     code; \
 487     j 3f; \
 488 2: \
 489     code; \
 490 3: \
 491     addi x4, x4, -1; \
 492     bne x4, x0, 1b; \
 493                   )
 494
 495 #define TEST_BR2_DIVERGED_FULL12( testnum, inst, n, result, code... )    \
 496   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 497     utidx x1; \
 498     sltiu x2, x1, 1; \
 499     add x3, x0, x0; \
 500     li x4, n; \
 501 1: \
 502     inst x2, x4, 2f; \
 503     addi x1, x1, -1; \
 504     sltiu x2, x1, 1; \
 505     j 1b; \
 506 2: \
 507     code; \
 508                  )
 509
 510 #define TEST_BR2_DIVERGED_FULL21( testnum, inst, n, result, code... )    \
 511   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 512     utidx x1; \
 513     sltiu x2, x1, 1; \
 514     add x3, x0, x0; \
 515     li x4, n; \
 516 1: \
 517     inst x4, x2, 2f; \
 518     addi x1, x1, -1; \
 519     sltiu x2, x1, 1; \
 520     j 1b; \
 521 2: \
 522     code; \
 523                  )
 524
 525 #define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
 526 test_ ## testnum: \
 527   vsetcfg nxreg,nfreg; \
 528   li a3,2048; \
 529   vsetvl a3,a3; \
 530   lui a0,%hi(vtcode ## testnum ); \
 531   vf %lo(vtcode ## testnum )(a0); \
 532   la a4,dst; \
 533   fence; \
 534   li a1,correctval; \
 535   li a2,0; \
 536   li TESTNUM, testnum; \
 537 test_loop ## testnum: \
 538   ld a0,0(a4); \
 539   beq a0,a1,skip ## testnum; \
 540   j fail; \
 541 skip ## testnum : \
 542   addi a4,a4,8; \
 543   addi a2,a2,1; \
 544   bne a2,a3,test_loop ## testnum; \
 545   j next ## testnum; \
 546 vtcode ## testnum : \
 547   code; \
 548   stop; \
 549 next ## testnum :
 550
 551 #define TEST_BR2_DIVERGED_MEM_FULL12( testnum, inst, n) \
 552   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 553     utidx x5; \
 554     slli x5, x5, 3; \
 555     la x6, dst; \
 556     add x5, x5, x6; \
 557     sd x0, 0(x5); \
 558     utidx x1; \
 559     sltiu x2, x1, 1; \
 560     li x4, n; \
 561 1: \
 562     inst x2, x4, 2f; \
 563     addi x1, x1, -1; \
 564     sltiu x2, x1, 1; \
 565     j 1b; \
 566 2: \
 567     ld x3, 0(x5); \
 568     addi x3, x3, 1; \
 569     sd x3, 0(x5); \
 570                  )
 571
 572 #define TEST_BR2_DIVERGED_MEM_FULL21( testnum, inst, n) \
 573   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 574     utidx x5; \
 575     slli x5, x5, 3; \
 576     la x6, dst; \
 577     add x5, x5, x6; \
 578     sd x0, 0(x5); \
 579     utidx x1; \
 580     sltiu x2, x1, 1; \
 581     li x4, n; \
 582 1: \
 583     inst x4, x2, 2f; \
 584     addi x1, x1, -1; \
 585     sltiu x2, x1, 1; \
 586     j 1b; \
 587 2: \
 588     ld x3, 0(x5); \
 589     addi x3, x3, 1; \
 590     sd x3, 0(x5); \
 591                  )
 592
 593 #-----------------------------------------------------------------------
 594 # Pass and fail code (assumes test num is in TESTNUM)
 595 #-----------------------------------------------------------------------
 596
 597 #define TEST_PASSFAIL \
 598         bne x0, TESTNUM, pass; \
 599 fail: \
 600         RVTEST_FAIL \
 601 pass: \
 602         RVTEST_PASS \
 603
 604
 605 #-----------------------------------------------------------------------
 606 # Test data section
 607 #-----------------------------------------------------------------------
 608
 609 #define TEST_DATA \
 610         .data; \
 611         .align 3; \
 612 dst: \
 613         .skip 16384; \
 614
 615 #endif