isa/macros/vector/test_macros.h

   1 #ifndef __TEST_MACROS_VECTOR_H
   2 #define __TEST_MACROS_VECTOR_H
   3
   4
   5 #-----------------------------------------------------------------------
   6 # Helper macros
   7 #-----------------------------------------------------------------------
   8
   9 #define TEST_CASE( testnum, testreg, correctval, code... ) \
  10   TEST_CASE_NREG( testnum, 32, 32, testreg, correctval, code )
  11
  12 # We use j fail, because for some cases branches are not enough to jump to fail
  13
  14 #define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
  15 test_ ## testnum: \
  16   li a3,2048; \
  17   vvcfgivl a3,a3,nxreg,nfreg; \
  18   lui a0,%hi(vtcode ## testnum ); \
  19   vf %lo(vtcode ## testnum )(a0); \
  20   la a4,dst; \
  21   vsd v ## testreg, a4; \
  22   fence.v.l; \
  23   li a1,correctval; \
  24   li a2,0; \
  25   li x28, testnum; \
  26 test_loop ## testnum: \
  27   ld a0,0(a4); \
  28   beq a0,a1,skip ## testnum; \
  29   j fail; \
  30 skip ## testnum : \
  31   addi a4,a4,8; \
  32   addi a2,a2,1; \
  33   bne a2,a3,test_loop ## testnum; \
  34   j next ## testnum; \
  35 vtcode ## testnum : \
  36   code; \
  37   stop; \
  38 next ## testnum :
  39
  40 # We use a macro hack to simpify code generation for various numbers
  41 # of bubble cycles.
  42
  43 #define TEST_INSERT_NOPS_0
  44 #define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
  45 #define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
  46 #define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
  47 #define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
  48 #define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
  49 #define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
  50 #define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
  51 #define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
  52 #define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
  53 #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
  54
  55
  56 #-----------------------------------------------------------------------
  57 # RV64UI MACROS
  58 #-----------------------------------------------------------------------
  59
  60 #-----------------------------------------------------------------------
  61 # Tests for instructions with immediate operand
  62 #-----------------------------------------------------------------------
  63
  64 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
  65     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  66       li  x1, val1; \
  67       inst x3, x1, imm; \
  68     )
  69
  70 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
  71     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  72       li  x1, val1; \
  73       inst x1, x1, imm; \
  74     )
  75
  76 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  77     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
  78       li  x1, val1; \
  79       inst x3, x1, imm; \
  80       TEST_INSERT_NOPS_ ## nop_cycles \
  81       addi  x4, x3, 0; \
  82     )
  83
  84 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
  85     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
  86       li  x1, val1; \
  87       TEST_INSERT_NOPS_ ## nop_cycles \
  88       inst x3, x1, imm; \
  89     )
  90
  91 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
  92     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
  93       inst x1, x0, imm; \
  94     )
  95
  96 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
  97     TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
  98       li  x1, val1; \
  99       inst x0, x1, imm; \
 100     )
 101
 102 #-----------------------------------------------------------------------
 103 # Tests for an instruction with register operands
 104 #-----------------------------------------------------------------------
 105
 106 #define TEST_R_OP( testnum, inst, result, val1 ) \
 107     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 108       li  x1, val1; \
 109       inst x3, x1; \
 110     )
 111
 112 #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
 113     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 114       li  x1, val1; \
 115       inst x1, x1; \
 116     )
 117
 118 #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
 119     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 120       li  x1, val1; \
 121       inst x3, x1; \
 122       TEST_INSERT_NOPS_ ## nop_cycles \
 123       addi  x4, x3, 0; \
 124     )
 125
 126 #-----------------------------------------------------------------------
 127 # Tests for an instruction with register-register operands
 128 #-----------------------------------------------------------------------
 129
 130 #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
 131     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 132       li  x1, val1; \
 133       li  x2, val2; \
 134       inst x3, x1, x2; \
 135     )
 136
 137 #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
 138     TEST_CASE_NREG( testnum, 3, 0, x1, result, \
 139       li  x1, val1; \
 140       li  x2, val2; \
 141       inst x1, x1, x2; \
 142     )
 143
 144 #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
 145     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 146       li  x1, val1; \
 147       li  x2, val2; \
 148       inst x2, x1, x2; \
 149     )
 150
 151 #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
 152     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 153       li  x1, val1; \
 154       inst x1, x1, x1; \
 155     )
 156
 157 #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
 158     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
 159       li  x1, val1; \
 160       li  x2, val2; \
 161       inst x3, x1, x2; \
 162       TEST_INSERT_NOPS_ ## nop_cycles \
 163       addi  x4, x3, 0; \
 164     )
 165
 166 #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 167     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 168       li  x1, val1; \
 169       TEST_INSERT_NOPS_ ## src1_nops \
 170       li  x2, val2; \
 171       TEST_INSERT_NOPS_ ## src2_nops \
 172       inst x3, x1, x2; \
 173     )
 174
 175 #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
 176     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
 177       li  x2, val2; \
 178       TEST_INSERT_NOPS_ ## src1_nops \
 179       li  x1, val1; \
 180       TEST_INSERT_NOPS_ ## src2_nops \
 181       inst x3, x1, x2; \
 182     )
 183
 184 #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
 185     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 186       li x1, val; \
 187       inst x2, x0, x1; \
 188     )
 189
 190 #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
 191     TEST_CASE_NREG( testnum, 3, 0, x2, result, \
 192       li x1, val; \
 193       inst x2, x1, x0; \
 194     )
 195
 196 #define TEST_RR_ZEROSRC12( testnum, inst, result ) \
 197     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
 198       inst x1, x0, x0; \
 199     )
 200
 201 #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
 202     TEST_CASE_NREG( testnum, 3, 0, x0, 0, \
 203       li x1, val1; \
 204       li x2, val2; \
 205       inst x0, x1, x2; \
 206     )
 207
 208
 209 #-----------------------------------------------------------------------
 210 # RV64UF MACROS
 211 #-----------------------------------------------------------------------
 212
 213 #-----------------------------------------------------------------------
 214 # Tests floating-point instructions
 215 #-----------------------------------------------------------------------
 216
 217 #define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 218 test_ ## testnum: \
 219   li a3,2048; \
 220   vvcfgivl a3,a3,nxreg,nfreg; \
 221   la  a5, test_ ## testnum ## _data ;\
 222   vflstw vf0, a5, x0; \
 223   addi a5,a5,4; \
 224   vflstw vf1, a5, x0; \
 225   addi a5,a5,4; \
 226   vflstw vf2, a5, x0; \
 227   addi a5,a5,4; \
 228   lui a0,%hi(vtcode ## testnum ); \
 229   vf %lo(vtcode ## testnum )(a0); \
 230   la a4,dst; \
 231   vsw vx1, a4; \
 232   fence.v.l; \
 233   lw  a1, 0(a5); \
 234   li a2, 0; \
 235   li x28, testnum; \
 236 test_loop ## testnum: \
 237   lw a0,0(a4); \
 238   beq a0,a1,skip ## testnum; \
 239   j fail; \
 240 skip ## testnum : \
 241   addi a4,a4,4; \
 242   addi a2,a2,1; \
 243   bne a2,a3,test_loop ## testnum; \
 244   b 1f; \
 245 vtcode ## testnum : \
 246   code; \
 247   stop; \
 248   .align 2; \
 249   test_ ## testnum ## _data: \
 250   .float val1; \
 251   .float val2; \
 252   .float val3; \
 253   .result; \
 254 1:
 255
 256 #define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
 257 test_ ## testnum: \
 258   li a3,2048; \
 259   vvcfgivl a3,a3,nxreg,nfreg; \
 260   la  a5, test_ ## testnum ## _data ;\
 261   vflstd vf0, a5, x0; \
 262   addi a5,a5,8; \
 263   vflstd vf1, a5, x0; \
 264   addi a5,a5,8; \
 265   vflstd vf2, a5, x0; \
 266   addi a5,a5,8; \
 267   lui a0,%hi(vtcode ## testnum ); \
 268   vf %lo(vtcode ## testnum )(a0); \
 269   la a4,dst; \
 270   vsd vx1, a4; \
 271   fence.v.l; \
 272   ld  a1, 0(a5); \
 273   li a2, 0; \
 274   li x28, testnum; \
 275 test_loop ## testnum: \
 276   ld a0,0(a4); \
 277   beq a0,a1,skip ## testnum; \
 278   j fail; \
 279 skip ## testnum : \
 280   addi a4,a4,8; \
 281   addi a2,a2,1; \
 282   bne a2,a3,test_loop ## testnum; \
 283   b 1f; \
 284 vtcode ## testnum : \
 285   code; \
 286   stop; \
 287   .align 3; \
 288   test_ ## testnum ## _data: \
 289   .double val1; \
 290   .double val2; \
 291   .double val3; \
 292   .result; \
 293 1:
 294
 295 #define TEST_FCVT_S_D( testnum, result, val1 ) \
 296   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, 0.0, 0.0, \
 297                     fcvt.s.d f3, f0; fcvt.d.s f3, f3; mftx.d x1, f3)
 298
 299 #define TEST_FCVT_D_S( testnum, result, val1 ) \
 300   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
 301                     fcvt.d.s f3, f0; fcvt.s.d f3, f3; mftx.s x1, f3)
 302
 303 #define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
 304   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
 305                     inst f3, f0, f1; mftx.s x1, f3)
 306
 307 #define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
 308   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
 309                     inst f3, f0, f1; mftx.d x1, f3)
 310
 311 #define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
 312   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
 313                     inst f3, f0, f1, f2; mftx.s x1, f3)
 314
 315 #define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
 316   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
 317                     inst f3, f0, f1, f2; mftx.d x1, f3)
 318
 319 #define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
 320   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
 321                     inst x1, f0, rm)
 322
 323 #define TEST_FP_INT_OP_D( testnum, inst, result, val1, rm ) \
 324   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, 0.0, 0.0, \
 325                     inst x1, f0, rm)
 326
 327 #define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
 328   TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, val2, 0.0, \
 329                     inst x1, f0, f1)
 330
 331 #define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
 332   TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, val2, 0.0, \
 333                     inst x1, f0, f1)
 334
 335 #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
 336 test_ ## testnum: \
 337   li a3,2048; \
 338   vvcfgivl a3,a3,2,1; \
 339   lui a0,%hi(vtcode ## testnum ); \
 340   vf %lo(vtcode ## testnum )(a0); \
 341   la a4,dst; \
 342   vsw vx1, a4; \
 343   fence.v.l; \
 344   la  a5, test_ ## testnum ## _data ;\
 345   lw  a1, 0(a5); \
 346   li a2, 0; \
 347   li x28, testnum; \
 348 test_loop ## testnum: \
 349   lw a0,0(a4); \
 350   beq a0,a1,skip ## testnum; \
 351   j fail; \
 352 skip ## testnum : \
 353   addi a4,a4,4; \
 354   addi a2,a2,1; \
 355   bne a2,a3,test_loop ## testnum; \
 356   b 1f; \
 357 vtcode ## testnum : \
 358   li x1, val1; \
 359   inst f0, x1; \
 360   mftx.s x1, f0; \
 361   stop; \
 362   .align 2; \
 363   test_ ## testnum ## _data: \
 364   .float result; \
 365 1:
 366
 367 #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
 368 test_ ## testnum: \
 369   li a3,2048; \
 370   vvcfgivl a3,a3,2,1; \
 371   lui a0,%hi(vtcode ## testnum ); \
 372   vf %lo(vtcode ## testnum )(a0); \
 373   la a4,dst; \
 374   vsd vx1, a4; \
 375   fence.v.l; \
 376   la  a5, test_ ## testnum ## _data ;\
 377   ld  a1, 0(a5); \
 378   li a2, 0; \
 379   li x28, testnum; \
 380 test_loop ## testnum: \
 381   ld a0,0(a4); \
 382   beq a0,a1,skip ## testnum; \
 383   j fail; \
 384 skip ## testnum : \
 385   addi a4,a4,8; \
 386   addi a2,a2,1; \
 387   bne a2,a3,test_loop ## testnum; \
 388   b 1f; \
 389 vtcode ## testnum : \
 390   li x1, val1; \
 391   inst f0, x1; \
 392   mftx.d x1, f0; \
 393   stop; \
 394   .align 3; \
 395   test_ ## testnum ## _data: \
 396   .double result; \
 397 1:
 398
 399
 400 #-----------------------------------------------------------------------
 401 # RV64UV MACROS
 402 #-----------------------------------------------------------------------
 403
 404 #-----------------------------------------------------------------------
 405 # Test branch instructions
 406 #-----------------------------------------------------------------------
 407
 408 #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2) \
 409     TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 410       li x1, val1; \
 411       li x2, val2; \
 412       add x3, x0, x0; \
 413       inst x1, x2, 2f; \
 414       addi x3, x3, 1; \
 415 1:    j 3f; \
 416       addi x3, x3, 4; \
 417 2:    inst x1, x2, 1b; \
 418       addi x3, x3, 2; \
 419 3: \
 420     )
 421
 422 #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
 423   TEST_CASE_NREG( testnum, 4, 0, x3, 0, \
 424     li  x1, val1; \
 425     li  x2, val2; \
 426     add x3, x0, x0; \
 427     inst x1, x2, 1f; \
 428     j 2f; \
 429 1:  addi x3, x3, 1; \
 430     j 3f; \
 431 2:  inst x1, x2, 1b; \
 432 3: \
 433                   )
 434
 435 #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 436   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 437     add x3, x0, x0; \
 438     li  x4, 0; \
 439 1:  li  x1, val1; \
 440     TEST_INSERT_NOPS_ ## src1_nops \
 441     li  x2, val2; \
 442     TEST_INSERT_NOPS_ ## src2_nops \
 443     inst x1, x2, 2f; \
 444     addi  x4, x4, 1; \
 445     li  x5, 2; \
 446     bne x4, x5, 1b; \
 447     j 3f; \
 448 2:  add x3, x3, 1; \
 449 3:  \
 450   )
 451
 452 #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
 453   TEST_CASE_NREG( testnum, 6, 0, x3, 0, \
 454     add x3, x0, x0; \
 455     li  x4, 0; \
 456 1:  li  x2, val2; \
 457     TEST_INSERT_NOPS_ ## src1_nops \
 458     li  x1, val1; \
 459     TEST_INSERT_NOPS_ ## src2_nops \
 460     inst x1, x2, 2f; \
 461     addi  x4, x4, 1; \
 462     li  x5, 2; \
 463     bne x4, x4, 1b; \
 464     j 3f; \
 465 2:  add x3, x3, 1; \
 466 3: \
 467                   )
 468
 469 #define TEST_BR2_DIVERGED_ODD_EVEN( testnum, inst, n, result, code...)   \
 470   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 471     utidx x1; \
 472     andi x2, x1, 1;\
 473     add x3, x0, x0; \
 474     li x4, n; \
 475 1: \
 476     beq x0, x2, 2f; \
 477     code; \
 478     j 3f; \
 479 2: \
 480     code; \
 481 3: \
 482     addi x4, x4, -1; \
 483     bne x4, x0, 1b; \
 484                   )
 485
 486 #define TEST_BR2_DIVERGED_FULL12( testnum, inst, n, result, code... )    \
 487   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 488     utidx x1; \
 489     sltiu x2, x1, 1; \
 490     add x3, x0, x0; \
 491     li x4, n; \
 492 1: \
 493     inst x2, x4, 2f; \
 494     addi x1, x1, -1; \
 495     sltiu x2, x1, 1; \
 496     j 1b; \
 497 2: \
 498     code; \
 499                  )
 500
 501 #define TEST_BR2_DIVERGED_FULL21( testnum, inst, n, result, code... )    \
 502   TEST_CASE_NREG( testnum, 5, 0, x3, result, \
 503     utidx x1; \
 504     sltiu x2, x1, 1; \
 505     add x3, x0, x0; \
 506     li x4, n; \
 507 1: \
 508     inst x4, x2, 2f; \
 509     addi x1, x1, -1; \
 510     sltiu x2, x1, 1; \
 511     j 1b; \
 512 2: \
 513     code; \
 514                  )
 515
 516 #define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
 517 test_ ## testnum: \
 518   li a3,2048; \
 519   vvcfgivl a3,a3,nxreg,nfreg; \
 520   lui a0,%hi(vtcode ## testnum ); \
 521   vf %lo(vtcode ## testnum )(a0); \
 522   la a4,dst; \
 523   fence.v.l; \
 524   li a1,correctval; \
 525   li a2,0; \
 526   li x28, testnum; \
 527 test_loop ## testnum: \
 528   ld a0,0(a4); \
 529   beq a0,a1,skip ## testnum; \
 530   j fail; \
 531 skip ## testnum : \
 532   addi a4,a4,8; \
 533   addi a2,a2,1; \
 534   bne a2,a3,test_loop ## testnum; \
 535   j next ## testnum; \
 536 vtcode ## testnum : \
 537   code; \
 538   stop; \
 539 next ## testnum :
 540
 541 #define TEST_BR2_DIVERGED_MEM_FULL12( testnum, inst, n) \
 542   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 543     utidx x5; \
 544     slli x5, x5, 3; \
 545     la x6, dst; \
 546     add x5, x5, x6; \
 547     sd x0, 0(x5); \
 548     utidx x1; \
 549     sltiu x2, x1, 1; \
 550     li x4, n; \
 551 1: \
 552     inst x2, x4, 2f; \
 553     addi x1, x1, -1; \
 554     sltiu x2, x1, 1; \
 555     j 1b; \
 556 2: \
 557     ld x3, 0(x5); \
 558     addi x3, x3, 1; \
 559     sd x3, 0(x5); \
 560                  )
 561
 562 #define TEST_BR2_DIVERGED_MEM_FULL21( testnum, inst, n) \
 563   TEST_CASE_NREG_MEM( testnum, 7, 0, 1, \
 564     utidx x5; \
 565     slli x5, x5, 3; \
 566     la x6, dst; \
 567     add x5, x5, x6; \
 568     sd x0, 0(x5); \
 569     utidx x1; \
 570     sltiu x2, x1, 1; \
 571     li x4, n; \
 572 1: \
 573     inst x4, x2, 2f; \
 574     addi x1, x1, -1; \
 575     sltiu x2, x1, 1; \
 576     j 1b; \
 577 2: \
 578     ld x3, 0(x5); \
 579     addi x3, x3, 1; \
 580     sd x3, 0(x5); \
 581                  )
 582
 583 #-----------------------------------------------------------------------
 584 # Pass and fail code (assumes test num is in x28)
 585 #-----------------------------------------------------------------------
 586
 587 #define TEST_PASSFAIL \
 588         bne x0, x28, pass; \
 589 fail: \
 590         RVTEST_FAIL \
 591 pass: \
 592         RVTEST_PASS \
 593
 594
 595 #-----------------------------------------------------------------------
 596 # Test data section
 597 #-----------------------------------------------------------------------
 598
 599 #define TEST_DATA \
 600         .data; \
 601         .align 3; \
 602 dst: \
 603         .skip 16384; \
 604
 605 #endif