isa/rv32si/fa_addr_zscale_8192.S

   1 #*****************************************************************************
   2 # fa_addr.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test fault load/store trap.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV32S
  12 RVTEST_CODE_BEGIN
  13
  14   li s0, 0x2000
  15   li s1, 1
  16
  17 loop:
  18   addi s1, s1, -1
  19
  20   la t0, evec_load
  21   csrw evec, t0
  22
  23   li TESTNUM, 2
  24   lw x0, 0(s0)
  25   j fail
  26
  27   li TESTNUM, 3
  28   lh x0, 0(s0)
  29   j fail
  30
  31   li TESTNUM, 4
  32   lhu x0, 0(s0)
  33   j fail
  34
  35   li TESTNUM, 5
  36   lb x0, 0(s0)
  37   j fail
  38
  39   li TESTNUM, 6
  40   lbu x0, 0(s0)
  41   j fail
  42
  43   la t0, evec_store
  44   csrw evec, t0
  45
  46   li TESTNUM, 7
  47   sw x0, 0(s0)
  48   j fail
  49
  50   li TESTNUM, 8
  51   sh x0, 0(s0)
  52   j fail
  53
  54   li TESTNUM, 9
  55   sb x0, 0(s0)
  56   j fail
  57
  58   li s0, 0xbad1dea0
  59   beq s1, x0, loop
  60
  61   j pass
  62
  63   TEST_PASSFAIL
  64
  65 evec_load:
  66   li t1, CAUSE_FAULT_LOAD
  67   csrr t0, cause
  68   bne t0, t1, fail
  69   csrr t0, epc
  70   addi t0, t0, 8
  71   csrw epc, t0
  72   sret
  73
  74 evec_store:
  75   li t1, CAUSE_FAULT_STORE
  76   csrr t0, cause
  77   bne t0, t1, fail
  78   csrr t0, epc
  79   addi t0, t0, 8
  80   csrw epc, t0
  81   sret
  82
  83 RVTEST_CODE_END
  84
  85   .data
  86 RVTEST_DATA_BEGIN
  87
  88   TEST_DATA
  89
  90 RVTEST_DATA_END