3bec030566f050367d6e704a02b65c9b1ac988ce
[riscv-tests.git] / isa / rv32si / illegal.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal instruction trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32S
14 RVTEST_CODE_BEGIN
15
16 la t0, stvec
17 csrw stvec, t0
18
19 li TESTNUM, 2
20 .word 0
21 j fail
22
23 j pass
24
25 TEST_PASSFAIL
26
27 stvec:
28 li t1, CAUSE_ILLEGAL_INSTRUCTION
29 csrr t0, scause
30 bne t0, t1, fail
31 csrr t0, sepc
32 addi t0, t0, 8
33 csrw sepc, t0
34 sret
35
36 RVTEST_CODE_END
37
38 .data
39 RVTEST_DATA_BEGIN
40
41 TEST_DATA
42
43 RVTEST_DATA_END