isa/rv32si/ma_addr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_addr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ld/st trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV32S
  14 RVTEST_CODE_BEGIN
  15
  16   la s0, stvec_load
  17
  18   la t0, stvec_load
  19   csrw stvec, t0
  20
  21   li TESTNUM, 2
  22   lw x0, 1(s0)
  23   j fail
  24
  25   li TESTNUM, 3
  26   lw x0, 2(s0)
  27   j fail
  28
  29   li TESTNUM, 4
  30   lw x0, 3(s0)
  31   j fail
  32
  33   li TESTNUM, 5
  34   lh x0, 1(s0)
  35   j fail
  36
  37   li TESTNUM, 6
  38   lhu x0, 1(s0)
  39   j fail
  40
  41   la t0, stvec_store
  42   csrw stvec, t0
  43
  44   li TESTNUM, 7
  45   sw x0, 1(s0)
  46   j fail
  47
  48   li TESTNUM, 8
  49   sw x0, 2(s0)
  50   j fail
  51
  52   li TESTNUM, 9
  53   sw x0, 3(s0)
  54   j fail
  55
  56   li TESTNUM, 10
  57   sh x0, 1(s0)
  58   j fail
  59
  60   j pass
  61
  62   TEST_PASSFAIL
  63
  64 stvec_load:
  65   li t1, CAUSE_MISALIGNED_LOAD
  66   csrr t0, scause
  67   bne t0, t1, fail
  68   csrr t0, sepc
  69   addi t0, t0, 8
  70   csrw sepc, t0
  71   sret
  72
  73 stvec_store:
  74   li t1, CAUSE_MISALIGNED_STORE
  75   csrr t0, scause
  76   bne t0, t1, fail
  77   csrr t0, sepc
  78   addi t0, t0, 8
  79   csrw sepc, t0
  80   sret
  81
  82 RVTEST_CODE_END
  83
  84   .data
  85 RVTEST_DATA_BEGIN
  86
  87   TEST_DATA
  88
  89 RVTEST_DATA_END