minor mt updates
[riscv-tests.git] / isa / rv32si / sbreak.S
1 #*****************************************************************************
2 # scall.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test syscall trap.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32S
12 RVTEST_CODE_BEGIN
13
14 la t0, evec
15 csrw evec, t0
16
17 li TESTNUM, 2
18 sbreak
19 j fail
20
21 j pass
22
23 TEST_PASSFAIL
24
25 evec:
26 li t1, CAUSE_BREAKPOINT
27 csrr t0, cause
28 bne t0, t1, fail
29 csrr t0, epc
30 addi t0, t0, 8
31 csrw epc, t0
32 sret
33
34 RVTEST_CODE_END
35
36 .data
37 RVTEST_DATA_BEGIN
38
39 TEST_DATA
40
41 RVTEST_DATA_END