Add LICENSE
[riscv-tests.git] / isa / rv32si / timer.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # timer.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test timer interrupt.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32S
14 RVTEST_CODE_BEGIN
15
16 la t0, evec
17 csrw evec, t0
18
19 csrr t0, count
20 add t0, t0, 1000
21 csrw compare, t0
22
23 li t1, 1<<23
24 csrs status, t1 # turn on timer IRQ 7
25 csrsi status, 4 # enable interrupts
26
27 li TESTNUM, 2
28 li a0,10000
29 loop:
30 div x0, x0, x0
31 addi a0, a0, -1
32 bne a0, x0, loop
33 j fail # assumption is that you can't divide in one cycle
34
35 TEST_PASSFAIL
36
37 evec:
38 li TESTNUM, 3
39 li t1, 0x80000000|IRQ_TIMER
40 csrr t0, cause
41 bne t0, t1, fail
42 j pass
43
44 RVTEST_CODE_END
45
46 .data
47 RVTEST_DATA_BEGIN
48
49 TEST_DATA
50
51 RVTEST_DATA_END