Remove instruction width assumptions to support RVC
[riscv-tests.git] / isa / rv32ua / lrsc.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # lrsr.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test LR/SC instructions.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32U
14 RVTEST_CODE_BEGIN
15
16 # get a unique core id
17 la a0, coreid
18 li a1, 1
19 amoadd.w a2, a1, (a0)
20
21 # for now, only run this on core 0
22 1:li a3, 1
23 bgeu a2, a3, 1b
24
25 1: lw a1, (a0)
26 bltu a1, a3, 1b
27
28 # make sure that sc without a reservation fails.
29 TEST_CASE( 2, a4, 1, \
30 la a0, foo; \
31 sc.w a4, x0, (a0); \
32 )
33
34 # make sure that sc with the wrong reservation fails.
35 # TODO is this actually mandatory behavior?
36 TEST_CASE( 3, a4, 1, \
37 la a0, foo; \
38 add a1, a0, 1024; \
39 lr.w a1, (a1); \
40 sc.w a4, a1, (a0); \
41 )
42
43 # have each core add its coreid to foo 1000 times
44 la a0, foo
45 li a1, 1000
46 1: lr.w a4, (a0)
47 add a4, a4, a2
48 sc.w a4, a4, (a0)
49 bnez a4, 1b
50 add a1, a1, -1
51 bnez a1, 1b
52
53 # wait for all cores to finish
54 la a0, barrier
55 li a1, 1
56 amoadd.w x0, a1, (a0)
57 1: lw a1, (a0)
58 blt a1, a3, 1b
59 fence
60
61 # expected result is 1000*ncores*(ncores-1)/2
62 TEST_CASE( 4, a2, 0, \
63 la a0, foo; \
64 li a1, 500; \
65 mul a1, a1, a3; \
66 add a2, a3, -1; \
67 mul a1, a1, a2; \
68 lw a2, (a0); \
69 sub a2, a2, a1; \
70 )
71
72 TEST_PASSFAIL
73
74 RVTEST_CODE_END
75
76 .data
77 RVTEST_DATA_BEGIN
78
79 TEST_DATA
80
81 coreid: .word 0
82 barrier: .word 0
83 foo: .word 0
84 RVTEST_DATA_END