ERET -> xRET; new memory map
[riscv-tests.git] / isa / rv32ui / add.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # add.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test add instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 );
21 TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 );
22 TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 );
23
24 TEST_RR_OP( 5, add, 0xffff8000, 0x00000000, 0xffff8000 );
25 TEST_RR_OP( 6, add, 0x80000000, 0x80000000, 0x00000000 );
26 TEST_RR_OP( 7, add, 0x7fff8000, 0x80000000, 0xffff8000 );
27
28 TEST_RR_OP( 8, add, 0x00007fff, 0x00000000, 0x00007fff );
29 TEST_RR_OP( 9, add, 0x7fffffff, 0x7fffffff, 0x00000000 );
30 TEST_RR_OP( 10, add, 0x80007ffe, 0x7fffffff, 0x00007fff );
31
32 TEST_RR_OP( 11, add, 0x80007fff, 0x80000000, 0x00007fff );
33 TEST_RR_OP( 12, add, 0x7fff7fff, 0x7fffffff, 0xffff8000 );
34
35 TEST_RR_OP( 13, add, 0xffffffff, 0x00000000, 0xffffffff );
36 TEST_RR_OP( 14, add, 0x00000000, 0xffffffff, 0x00000001 );
37 TEST_RR_OP( 15, add, 0xfffffffe, 0xffffffff, 0xffffffff );
38
39 TEST_RR_OP( 16, add, 0x80000000, 0x00000001, 0x7fffffff );
40
41 #-------------------------------------------------------------
42 # Source/Destination tests
43 #-------------------------------------------------------------
44
45 TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
46 TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
47 TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
48
49 #-------------------------------------------------------------
50 # Bypassing tests
51 #-------------------------------------------------------------
52
53 TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
54 TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
55 TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
56
57 TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
58 TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
59 TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
60 TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
61 TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
62 TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
63
64 TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
65 TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
66 TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
67 TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
68 TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
69 TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
70
71 TEST_RR_ZEROSRC1( 35, add, 15, 15 );
72 TEST_RR_ZEROSRC2( 36, add, 32, 32 );
73 TEST_RR_ZEROSRC12( 37, add, 0 );
74 TEST_RR_ZERODEST( 38, add, 16, 30 );
75
76 TEST_PASSFAIL
77
78 RVTEST_CODE_END
79
80 .data
81 RVTEST_DATA_BEGIN
82
83 TEST_DATA
84
85 RVTEST_DATA_END