srl and srai
[riscv-tests.git] / isa / rv32ui / addi.S
1 #*****************************************************************************
2 # addi.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test addi instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32U
12 RVTEST_CODE_BEGIN
13
14 #-------------------------------------------------------------
15 # Arithmetic tests
16 #-------------------------------------------------------------
17
18 TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 );
19 TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 );
20 TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 );
21
22 TEST_IMM_OP( 5, addi, 0xfffff800, 0x00000000, 0x800 );
23 TEST_IMM_OP( 6, addi, 0x80000000, 0x80000000, 0x000 );
24 TEST_IMM_OP( 7, addi, 0x7ffff800, 0x80000000, 0x800 );
25
26 TEST_IMM_OP( 8, addi, 0x000007ff, 0x00000000, 0x7ff );
27 TEST_IMM_OP( 9, addi, 0x7fffffff, 0x7fffffff, 0x000 );
28 TEST_IMM_OP( 10, addi, 0x800007fe, 0x7fffffff, 0x7ff );
29
30 TEST_IMM_OP( 11, addi, 0x800007ff, 0x80000000, 0x7ff );
31 TEST_IMM_OP( 12, addi, 0x7ffff7ff, 0x7fffffff, 0x800 );
32
33 TEST_IMM_OP( 13, addi, 0xffffffff, 0x00000000, 0xfff );
34 TEST_IMM_OP( 14, addi, 0x00000000, 0xffffffff, 0x001 );
35 TEST_IMM_OP( 15, addi, 0xfffffffe, 0xffffffff, 0xfff );
36
37 TEST_IMM_OP( 16, addi, 0x80000000, 0x7fffffff, 0x001 );
38
39 #-------------------------------------------------------------
40 # Source/Destination tests
41 #-------------------------------------------------------------
42
43 TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
44
45 #-------------------------------------------------------------
46 # Bypassing tests
47 #-------------------------------------------------------------
48
49 TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
50 TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
51 TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 );
52
53 TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
54 TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
55 TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 );
56
57 TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
58 TEST_IMM_ZERODEST( 25, addi, 33, 50 );
59
60 TEST_PASSFAIL
61
62 RVTEST_CODE_END
63
64 .data
65 RVTEST_DATA_BEGIN
66
67 TEST_DATA
68
69 RVTEST_DATA_END