Fixed srl, srli
[riscv-tests.git] / isa / rv32ui / jal.S
1 #*****************************************************************************
2 # jal.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test jal instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32U
12 RVTEST_CODE_BEGIN
13
14 #-------------------------------------------------------------
15 # Test 2: Basic test
16 #-------------------------------------------------------------
17
18 test_2:
19 li x28, 2
20 li ra, 0
21
22 linkaddr_2:
23 jal target_2
24 nop
25 nop
26
27 j fail
28
29 target_2:
30 la x2, linkaddr_2
31 addi x2, x2, 4
32 bne x2, ra, fail
33
34 #-------------------------------------------------------------
35 # Test delay slot instructions not executed nor bypassed
36 #-------------------------------------------------------------
37
38 TEST_CASE( 3, x2, 3, \
39 li x2, 1; \
40 jal 1f; \
41 addi x2, x2, 1; \
42 addi x2, x2, 1; \
43 addi x2, x2, 1; \
44 addi x2, x2, 1; \
45 1: addi x2, x2, 1; \
46 addi x2, x2, 1; \
47 )
48
49 TEST_PASSFAIL
50
51 RVTEST_CODE_END
52
53 .data
54 RVTEST_DATA_BEGIN
55
56 TEST_DATA
57
58 RVTEST_DATA_END