Fixed srl, srli
[riscv-tests.git] / isa / rv32ui / jalr.S
1 #*****************************************************************************
2 # jalr.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test jalr instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32U
12 RVTEST_CODE_BEGIN
13
14 #-------------------------------------------------------------
15 # Test 2: Basic test
16 #-------------------------------------------------------------
17
18 test_2:
19 li x28, 2
20 li x31, 0
21 la x2, target_2
22
23 linkaddr_2:
24 jalr x19, x2, 0
25 nop
26 nop
27
28 j fail
29
30 target_2:
31 la x1, linkaddr_2
32 addi x1, x1, 4
33 bne x1, x19, fail
34
35 #-------------------------------------------------------------
36 # Test 3: Check r0 target and that r31 is not modified
37 #-------------------------------------------------------------
38
39 test_3:
40 li x28, 3
41 li x31, 0
42 la x3, target_3
43
44 linkaddr_3:
45 jalr x0, x3, 0
46 nop
47
48 j fail
49
50 target_3:
51 bne x31, x0, fail
52
53 #-------------------------------------------------------------
54 # Bypassing tests
55 #-------------------------------------------------------------
56
57 TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
58 TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
59 TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
60
61 #-------------------------------------------------------------
62 # Test delay slot instructions not executed nor bypassed
63 #-------------------------------------------------------------
64
65 TEST_CASE( 7, x1, 4, \
66 li x1, 1; \
67 la x2, 1f;
68 jalr x19, x2, -4; \
69 addi x1, x1, 1; \
70 addi x1, x1, 1; \
71 addi x1, x1, 1; \
72 addi x1, x1, 1; \
73 1: addi x1, x1, 1; \
74 addi x1, x1, 1; \
75 )
76
77 TEST_PASSFAIL
78
79 RVTEST_CODE_END
80
81 .data
82 RVTEST_DATA_BEGIN
83
84 TEST_DATA
85
86 RVTEST_DATA_END