isa/rv32ui/lrsc.S

   1 #*****************************************************************************
   2 # lrsr.S
   3 #-----------------------------------------------------------------------------
   4 #
   5 # Test LR/SC instructions.
   6 #
   7
   8 #include "riscv_test.h"
   9 #include "test_macros.h"
  10
  11 RVTEST_RV32U
  12 RVTEST_CODE_BEGIN
  13
  14 # wait for all cores to boot
  15 la a0, coreid
  16 li a1, 1
  17 amoadd.w a2, a1, (a0)
  18 lw a3, 4(x0)
  19 1: lw a1, (a0)
  20 blt a1, a3, 1b
  21
  22 # make sure that sc without a reservation fails.
  23 TEST_CASE( 2, a4, 1, \
  24   la a0, foo; \
  25   sc.w a4, x0, (a0); \
  26 )
  27
  28 # make sure that sc with the wrong reservation fails.
  29 TEST_CASE( 3, a4, 1, \
  30   la a0, foo; \
  31   add a1, a0, 1024; \
  32   lr.w a1, (a1); \
  33   sc.w a4, a1, (a0); \
  34 )
  35
  36 # have each core add its coreid to foo 1000 times
  37 la a0, foo
  38 li a1, 1000
  39 1: lr.w a4, (a0)
  40 add a4, a4, a2
  41 sc.w a4, a4, (a0)
  42 bnez a4, 1b
  43 add a1, a1, -1
  44 bnez a1, 1b
  45
  46 # wait for all cores to finish
  47 la a0, barrier
  48 li a1, 1
  49 amoadd.w x0, a1, (a0)
  50 1: lw a1, (a0)
  51 blt a1, a3, 1b
  52 fence
  53
  54 # expected result is 1000*ncores*(ncores-1)/2
  55 TEST_CASE( 4, a2, 0, \
  56   la a0, foo; \
  57   li a1, 500; \
  58   mul a1, a1, a3; \
  59   add a2, a3, -1; \
  60   mul a1, a1, a2; \
  61   lw a2, (a0); \
  62   sub a2, a2, a1; \
  63 )
  64
  65 TEST_PASSFAIL
  66
  67 RVTEST_CODE_END
  68
  69   .data
  70 RVTEST_DATA_BEGIN
  71
  72   TEST_DATA
  73
  74 coreid: .word 0
  75 barrier: .word 0
  76 foo: .word 0
  77 RVTEST_DATA_END