isa/rv32ui/lrsc.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # lrsr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test LR/SC instructions.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV32U
  14 RVTEST_CODE_BEGIN
  15
  16 # get a unique core id
  17 la a0, coreid
  18 li a1, 1
  19 amoadd.w a2, a1, (a0)
  20
  21 # for now, only run this on core 0
  22 1:li a3, 1
  23 bgeu a2, a3, 1b
  24
  25 1: lw a1, (a0)
  26 bltu a1, a3, 1b
  27
  28 # make sure that sc without a reservation fails.
  29 TEST_CASE( 2, a4, 1, \
  30   la a0, foo; \
  31   sc.w a4, x0, (a0); \
  32 )
  33
  34 # make sure that sc with the wrong reservation fails.
  35 TEST_CASE( 3, a4, 1, \
  36   la a0, foo; \
  37   add a1, a0, 1024; \
  38   lr.w a1, (a1); \
  39   sc.w a4, a1, (a0); \
  40 )
  41
  42 # have each core add its coreid to foo 1000 times
  43 la a0, foo
  44 li a1, 1000
  45 1: lr.w a4, (a0)
  46 add a4, a4, a2
  47 sc.w a4, a4, (a0)
  48 bnez a4, 1b
  49 add a1, a1, -1
  50 bnez a1, 1b
  51
  52 # wait for all cores to finish
  53 la a0, barrier
  54 li a1, 1
  55 amoadd.w x0, a1, (a0)
  56 1: lw a1, (a0)
  57 blt a1, a3, 1b
  58 fence
  59
  60 # expected result is 1000*ncores*(ncores-1)/2
  61 TEST_CASE( 4, a2, 0, \
  62   la a0, foo; \
  63   li a1, 500; \
  64   mul a1, a1, a3; \
  65   add a2, a3, -1; \
  66   mul a1, a1, a2; \
  67   lw a2, (a0); \
  68   sub a2, a2, a1; \
  69 )
  70
  71 TEST_PASSFAIL
  72
  73 RVTEST_CODE_END
  74
  75   .data
  76 RVTEST_DATA_BEGIN
  77
  78   TEST_DATA
  79
  80 coreid: .word 0
  81 barrier: .word 0
  82 foo: .word 0
  83 RVTEST_DATA_END