isa/rv32ui/lrsc.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # lrsr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test LR/SC instructions.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV32U
  14 RVTEST_CODE_BEGIN
  15
  16 # wait for all cores to boot
  17 la a0, coreid
  18 li a1, 1
  19 amoadd.w a2, a1, (a0)
  20 lw a3, 4(x0)
  21 1: lw a1, (a0)
  22 blt a1, a3, 1b
  23
  24 # make sure that sc without a reservation fails.
  25 TEST_CASE( 2, a4, 1, \
  26   la a0, foo; \
  27   sc.w a4, x0, (a0); \
  28 )
  29
  30 # make sure that sc with the wrong reservation fails.
  31 TEST_CASE( 3, a4, 1, \
  32   la a0, foo; \
  33   add a1, a0, 1024; \
  34   lr.w a1, (a1); \
  35   sc.w a4, a1, (a0); \
  36 )
  37
  38 # have each core add its coreid to foo 1000 times
  39 la a0, foo
  40 li a1, 1000
  41 1: lr.w a4, (a0)
  42 add a4, a4, a2
  43 sc.w a4, a4, (a0)
  44 bnez a4, 1b
  45 add a1, a1, -1
  46 bnez a1, 1b
  47
  48 # wait for all cores to finish
  49 la a0, barrier
  50 li a1, 1
  51 amoadd.w x0, a1, (a0)
  52 1: lw a1, (a0)
  53 blt a1, a3, 1b
  54 fence
  55
  56 # expected result is 1000*ncores*(ncores-1)/2
  57 TEST_CASE( 4, a2, 0, \
  58   la a0, foo; \
  59   li a1, 500; \
  60   mul a1, a1, a3; \
  61   add a2, a3, -1; \
  62   mul a1, a1, a2; \
  63   lw a2, (a0); \
  64   sub a2, a2, a1; \
  65 )
  66
  67 TEST_PASSFAIL
  68
  69 RVTEST_CODE_END
  70
  71   .data
  72 RVTEST_DATA_BEGIN
  73
  74   TEST_DATA
  75
  76 coreid: .word 0
  77 barrier: .word 0
  78 foo: .word 0
  79 RVTEST_DATA_END