Better coverage of mul high instructions
[riscv-tests.git] / isa / rv32ui / mul.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # mul.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test mul instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
21 TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
22
23 TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
24 TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
25 TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
26
27 TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
28 TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
29 TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
30
31 TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
32 TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
33
34 TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
35
36 TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
37 TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
38 TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
39
40 #-------------------------------------------------------------
41 # Source/Destination tests
42 #-------------------------------------------------------------
43
44 TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
45 TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
46 TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
47
48 #-------------------------------------------------------------
49 # Bypassing tests
50 #-------------------------------------------------------------
51
52 TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
53 TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
54 TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
55
56 TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
57 TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
58 TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
59 TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
60 TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
61 TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
62
63 TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
64 TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
65 TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
66 TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
67 TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
68 TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
69
70 TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
71 TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
72 TEST_RR_ZEROSRC12( 28, mul, 0 );
73 TEST_RR_ZERODEST( 29, mul, 33, 34 );
74
75 TEST_PASSFAIL
76
77 RVTEST_CODE_END
78
79 .data
80 RVTEST_DATA_BEGIN
81
82 TEST_DATA
83
84 RVTEST_DATA_END