Fixed srl, srli
[riscv-tests.git] / isa / rv32ui / rem.S
1 #*****************************************************************************
2 # rem.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test rem instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32U
12 RVTEST_CODE_BEGIN
13
14 #-------------------------------------------------------------
15 # Arithmetic tests
16 #-------------------------------------------------------------
17
18 TEST_RR_OP( 2, rem, 2, 20, 6 );
19 TEST_RR_OP( 3, rem, -2, -20, 6 );
20 TEST_RR_OP( 4, rem, 2, 20, -6 );
21 TEST_RR_OP( 5, rem, -2, -20, -6 );
22
23 TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
24 TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
25
26 TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
27 TEST_RR_OP( 9, rem, 1, 1, 0 );
28 TEST_RR_OP(10, rem, 0, 0, 0 );
29
30 TEST_PASSFAIL
31
32 RVTEST_CODE_END
33
34 .data
35 RVTEST_DATA_BEGIN
36
37 TEST_DATA
38
39 RVTEST_DATA_END