Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git] / isa / rv32ui / sll.S
1 #*****************************************************************************
2 # sll.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test sll instruction.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV32U
12 RVTEST_CODE_BEGIN
13
14 #-------------------------------------------------------------
15 # Arithmetic tests
16 #-------------------------------------------------------------
17
18 TEST_RR_OP( 2, sll, 0x00000001, 0x00000001, 0 );
19 TEST_RR_OP( 3, sll, 0x00000002, 0x00000001, 1 );
20 TEST_RR_OP( 4, sll, 0x00000080, 0x00000001, 7 );
21 TEST_RR_OP( 5, sll, 0x00004000, 0x00000001, 14 );
22 TEST_RR_OP( 6, sll, 0x80000000, 0x00000001, 31 );
23
24 TEST_RR_OP( 7, sll, 0xffffffff, 0xffffffff, 0 );
25 TEST_RR_OP( 8, sll, 0xfffffffe, 0xffffffff, 1 );
26 TEST_RR_OP( 9, sll, 0xffffff80, 0xffffffff, 7 );
27 TEST_RR_OP( 10, sll, 0xffffc000, 0xffffffff, 14 );
28 TEST_RR_OP( 11, sll, 0x80000000, 0xffffffff, 31 );
29
30 TEST_RR_OP( 12, sll, 0x21212121, 0x21212121, 0 );
31 TEST_RR_OP( 13, sll, 0x42424242, 0x21212121, 1 );
32 TEST_RR_OP( 14, sll, 0x90909080, 0x21212121, 7 );
33 TEST_RR_OP( 15, sll, 0x48484000, 0x21212121, 14 );
34 TEST_RR_OP( 16, sll, 0x80000000, 0x21212121, 31 );
35
36 # Verify that shifts only use bottom five bits
37
38 TEST_RR_OP( 17, sll, 0x21212121, 0x21212121, 0xffffffe0 );
39 TEST_RR_OP( 18, sll, 0x42424242, 0x21212121, 0xffffffe1 );
40 TEST_RR_OP( 19, sll, 0x90909080, 0x21212121, 0xffffffe7 );
41 TEST_RR_OP( 20, sll, 0x48484000, 0x21212121, 0xffffffee );
42 TEST_RR_OP( 21, sll, 0x00000000, 0x21212120, 0xffffffff );
43
44 #-------------------------------------------------------------
45 # Source/Destination tests
46 #-------------------------------------------------------------
47
48 TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 );
49 TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
50 TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
51
52 #-------------------------------------------------------------
53 # Bypassing tests
54 #-------------------------------------------------------------
55
56 TEST_RR_DEST_BYPASS( 25, 0, sll, 0x00000080, 0x00000001, 7 );
57 TEST_RR_DEST_BYPASS( 26, 1, sll, 0x00004000, 0x00000001, 14 );
58 TEST_RR_DEST_BYPASS( 27, 2, sll, 0x80000000, 0x00000001, 31 );
59
60 TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x00000080, 0x00000001, 7 );
61 TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x00004000, 0x00000001, 14 );
62 TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x80000000, 0x00000001, 31 );
63 TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x00000080, 0x00000001, 7 );
64 TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x00004000, 0x00000001, 14 );
65 TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x80000000, 0x00000001, 31 );
66
67 TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x00000080, 0x00000001, 7 );
68 TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x00004000, 0x00000001, 14 );
69 TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x80000000, 0x00000001, 31 );
70 TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x00000080, 0x00000001, 7 );
71 TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x00004000, 0x00000001, 14 );
72 TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x80000000, 0x00000001, 31 );
73
74 TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
75 TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
76 TEST_RR_ZEROSRC12( 42, sll, 0 );
77 TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
78
79 TEST_PASSFAIL
80
81 RVTEST_CODE_END
82
83 .data
84 RVTEST_DATA_BEGIN
85
86 TEST_DATA
87
88 RVTEST_DATA_END