isa/rv32ui/srl.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # srl.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test srl instruction.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV32U
  14 RVTEST_CODE_BEGIN
  15
  16   #-------------------------------------------------------------
  17   # Arithmetic tests
  18   #-------------------------------------------------------------
  19
  20   TEST_RR_OP( 2,  srl, 0xffff8000, 0xffff8000, 0  );
  21   TEST_RR_OP( 3,  srl, 0x7fffc000, 0xffff8000, 1  );
  22   TEST_RR_OP( 4,  srl, 0x01ffff00, 0xffff8000, 7  );
  23   TEST_RR_OP( 5,  srl, 0x0003fffe, 0xffff8000, 14 );
  24   TEST_RR_OP( 6,  srl, 0x0001ffff, 0xffff8001, 15 );
  25
  26   TEST_RR_OP( 7,  srl, 0xffffffff, 0xffffffff, 0  );
  27   TEST_RR_OP( 8,  srl, 0x7fffffff, 0xffffffff, 1  );
  28   TEST_RR_OP( 9,  srl, 0x01ffffff, 0xffffffff, 7  );
  29   TEST_RR_OP( 10, srl, 0x0003ffff, 0xffffffff, 14 );
  30   TEST_RR_OP( 11, srl, 0x00000001, 0xffffffff, 31 );
  31
  32   TEST_RR_OP( 12, srl, 0x21212121, 0x21212121, 0  );
  33   TEST_RR_OP( 13, srl, 0x10909090, 0x21212121, 1  );
  34   TEST_RR_OP( 14, srl, 0x00424242, 0x21212121, 7  );
  35   TEST_RR_OP( 15, srl, 0x00008484, 0x21212121, 14 );
  36   TEST_RR_OP( 16, srl, 0x00000000, 0x21212121, 31 );
  37
  38   # Verify that shifts only use bottom five bits
  39
  40   TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffe0 );
  41   TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffe1 );
  42   TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffe7 );
  43   TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffee );
  44   TEST_RR_OP( 21, srl, 0x00000000, 0x21212121, 0xffffffff );
  45
  46   #-------------------------------------------------------------
  47   # Source/Destination tests
  48   #-------------------------------------------------------------
  49
  50   TEST_RR_SRC1_EQ_DEST( 22, srl, 0x7fffc000, 0xffff8000, 1  );
  51   TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffe, 0xffff8000, 14 );
  52   TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
  53
  54   #-------------------------------------------------------------
  55   # Bypassing tests
  56   #-------------------------------------------------------------
  57
  58   TEST_RR_DEST_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1  );
  59   TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
  60   TEST_RR_DEST_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
  61
  62   TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x7fffc000, 0xffff8000, 1  );
  63   TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
  64   TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
  65   TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x7fffc000, 0xffff8000, 1  );
  66   TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
  67   TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
  68
  69   TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x7fffc000, 0xffff8000, 1  );
  70   TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
  71   TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
  72   TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x7fffc000, 0xffff8000, 1  );
  73   TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
  74   TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
  75
  76   TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
  77   TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
  78   TEST_RR_ZEROSRC12( 42, srl, 0 );
  79   TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
  80
  81   TEST_PASSFAIL
  82
  83 RVTEST_CODE_END
  84
  85   .data
  86 RVTEST_DATA_BEGIN
  87
  88   TEST_DATA
  89
  90 RVTEST_DATA_END