Fix ./configure in root
[riscv-tests.git] / isa / rv32ui / srli.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # srli.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test srli instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 TEST_IMM_OP( 2, srli, 0xffff8000, 0xffff8000, 0 );
21 TEST_IMM_OP( 3, srli, 0x7fffc000, 0xffff8000, 1 );
22 TEST_IMM_OP( 4, srli, 0x01ffff00, 0xffff8000, 7 );
23 TEST_IMM_OP( 5, srli, 0x0003fffe, 0xffff8000, 14 );
24 TEST_IMM_OP( 6, srli, 0x0001ffff, 0xffff8001, 15 );
25
26 TEST_IMM_OP( 7, srli, 0xffffffff, 0xffffffff, 0 );
27 TEST_IMM_OP( 8, srli, 0x7fffffff, 0xffffffff, 1 );
28 TEST_IMM_OP( 9, srli, 0x01ffffff, 0xffffffff, 7 );
29 TEST_IMM_OP( 10, srli, 0x0003ffff, 0xffffffff, 14 );
30 TEST_IMM_OP( 11, srli, 0x00000001, 0xffffffff, 31 );
31
32 TEST_IMM_OP( 12, srli, 0x21212121, 0x21212121, 0 );
33 TEST_IMM_OP( 13, srli, 0x10909090, 0x21212121, 1 );
34 TEST_IMM_OP( 14, srli, 0x00424242, 0x21212121, 7 );
35 TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 );
36 TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 );
37
38 #-------------------------------------------------------------
39 # Source/Destination tests
40 #-------------------------------------------------------------
41
42 TEST_IMM_SRC1_EQ_DEST( 21, srli, 0x7fffc000, 0xffff8000, 1 );
43
44 #-------------------------------------------------------------
45 # Bypassing tests
46 #-------------------------------------------------------------
47
48 TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 );
49 TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 );
50 TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 );
51
52 TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
53 TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
54 TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
55
56
57 TEST_IMM_ZEROSRC1( 28, srli, 0, 31 );
58 TEST_IMM_ZERODEST( 29, srli, 33, 20 );
59
60 TEST_PASSFAIL
61
62 RVTEST_CODE_END
63
64 .data
65 RVTEST_DATA_BEGIN
66
67 TEST_DATA
68
69 RVTEST_DATA_END