Remove instruction width assumptions to support RVC
[riscv-tests.git] / isa / rv32um / divu.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # divu.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test divu instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 TEST_RR_OP( 2, divu, 3, 20, 6 );
21 TEST_RR_OP( 3, divu, 715827879, -20, 6 );
22 TEST_RR_OP( 4, divu, 0, 20, -6 );
23 TEST_RR_OP( 5, divu, 0, -20, -6 );
24
25 TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
26 TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
27
28 TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
29 TEST_RR_OP( 9, divu, -1, 1, 0 );
30 TEST_RR_OP(10, divu, -1, 0, 0 );
31
32 TEST_PASSFAIL
33
34 RVTEST_CODE_END
35
36 .data
37 RVTEST_DATA_BEGIN
38
39 TEST_DATA
40
41 RVTEST_DATA_END