Mark RV32 tests as such
[riscv-tests.git] / isa / rv32um / mulhu.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # mulhu.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test mulhu instruction.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV32U
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
21 TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
22 TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
23
24 TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
25 TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
26 TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
27
28 TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
29 TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
30
31 TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
32
33 TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
34 TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
35 TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
36
37 #-------------------------------------------------------------
38 # Source/Destination tests
39 #-------------------------------------------------------------
40
41 TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
42 TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
43 TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
44
45 #-------------------------------------------------------------
46 # Bypassing tests
47 #-------------------------------------------------------------
48
49 TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
50 TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
51 TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
52
53 TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
54 TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
55 TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
56 TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
57 TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
58 TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
59
60 TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
61 TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
62 TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
63 TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
64 TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
65 TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
66
67 TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
68 TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
69 TEST_RR_ZEROSRC12( 28, mulhu, 0 );
70 TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
71
72
73 TEST_PASSFAIL
74
75 RVTEST_CODE_END
76
77 .data
78 RVTEST_DATA_BEGIN
79
80 TEST_DATA
81
82 RVTEST_DATA_END