isa/rv64mi/breakpoint.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # breakpoint.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test breakpoints, if they are implemented.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   # Set up breakpoint to trap on M-mode fetches.
  17   li TESTNUM, 2
  18   csrw tdrselect, x0
  19   la t2, 1f
  20   csrw tdrdata2, t2
  21   li t0, (BPCONTROL_MATCHCOND & (BPCONTROL_MATCHCOND>>1)) | BPCONTROL_M | BPCONTROL_X
  22   csrw tdrdata1, t0
  23   # Skip if breakpoint type is unsupported.
  24   csrr t1, tdrdata1
  25   bne t0, t1, 2f
  26 1:
  27   # Trap handler should skip this instruction.
  28   j fail
  29
  30   # Make sure reads don't trap.
  31   li TESTNUM, 3
  32   lw t0, (t2)
  33
  34 2:
  35   # Set up breakpoint to trap on M-mode reads.
  36   li TESTNUM, 4
  37   li t0, (BPCONTROL_MATCHCOND & (BPCONTROL_MATCHCOND>>1)) | BPCONTROL_M | BPCONTROL_R
  38   csrw tdrdata1, t0
  39   # Skip if breakpoint type is unsupported.
  40   csrr t1, tdrdata1
  41   bne t0, t1, 2f
  42   la t2, write_data
  43   csrw tdrdata2, t2
  44
  45   # Trap handler should skip this instruction.
  46   lw t2, (t2)
  47   beqz t2, fail
  48
  49   # Make sure writes don't trap.
  50   li TESTNUM, 5
  51   sw x0, (t2)
  52
  53 2:
  54   # Set up breakpoint to trap on M-mode stores.
  55   li TESTNUM, 6
  56   li t0, (BPCONTROL_MATCHCOND & (BPCONTROL_MATCHCOND>>1)) | BPCONTROL_M | BPCONTROL_W
  57   csrw tdrdata1, t0
  58   # Skip if breakpoint type is unsupported.
  59   csrr t1, tdrdata1
  60   bne t0, t1, 2f
  61
  62   # Trap handler should skip this instruction.
  63   sw t2, (t2)
  64
  65   # Make sure store didn't succeed.
  66   li TESTNUM, 7
  67   lw t2, (t2)
  68   bnez t2, fail
  69
  70 2:
  71   TEST_PASSFAIL
  72
  73 mtvec_handler:
  74   # Only even-numbered tests should trap.
  75   andi a0, TESTNUM, 1
  76   bnez a0, fail
  77
  78   li a0, CAUSE_BREAKPOINT
  79   csrr a1, mcause
  80   bne a0, a1, fail
  81
  82   csrr a0, mepc
  83   addi a0, a0, 4
  84   csrw mepc, a0
  85   mret
  86
  87 RVTEST_CODE_END
  88
  89   .data
  90 RVTEST_DATA_BEGIN
  91
  92   TEST_DATA
  93
  94 write_data: .word 0
  95
  96 RVTEST_DATA_END